6
Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
-100
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2064VE v.0.0
1
3
2
1
tsu2 + tco1
( )
MAX.
DESCRIPTION#PARAMETER
A1Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 ns
t
pd2
A2Data Propagation Delay – ns
f
max
A3Clock Frequency with Internal Feedback 100 – MHz
f
max (Ext.)
–4Clock Frequency with External Feedback – MHz
f
max (Tog.)
–5Clock Frequency, Max. Toggle – MHz
t
su1
–6GLB Reg. Setup Time before Clock, 4 PT Bypass – ns
t
co1
A7GLB Reg. Clock to Output Delay, ORP Bypass – ns
t
h1
–8GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 ns
t
su2
–9GLB Reg. Setup Time before Clock 8.0 ns
t
co2
A10GLB Reg. Clock to Output Delay – ns
t
h2
–11GLB Reg. Hold Time after Clock 0.0 ns
t
r1
A12Ext. Reset Pin to Output Delay, ORP Bypass – ns
t
rw1
–13Ext. Reset Pulse Duration 6.5 ns
t
ptoeen
B14Input to Output Enable – ns
t
ptoedis
C15Input to Output Disable – ns
t
goeen
B16Global OE Output Enable – ns
t
goedis
C17Global OE Output Disable – ns
t
wh
–18External Synchronous Clock Pulse Duration, High 5.0 – ns
t
wl
–19External Synchronous Clock Pulse Duration, Low 5.0 – ns
77
100
6.5
5.0
–
–
6.0
–
12.5
–
15.0
15.0
9.0
9.0
13.0
-135
MIN. MAX.
– 7.5
–
135 –
–
–
–
–
0.0
6.0
–
0.0
–
5.0
–
–
–
–
3.5 –
3.5 –
100
143
5.0
4.0
–
–
5.0
–
9.0
–
12.0
12.0
7.0
7.0
10.0