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September 15, 2011
Timing Diagrams
FIGURE 19. STANDARD (NTSC INPUT) TIMING
See Figures 20 and 21
See Figure 22
NOTES:
6. Signal 1a drawing reproduced with permission from EIA.
7. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
8. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a
propagation delay.
9. Odd-even output is low for even field, and high for odd field.
10. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that
for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with
propagation delay).
(Note 7)
(Note 8)
(Note 9)
(Note 10)
(Note 6)
Note 6
EL1881
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FN7018.2
September 15, 2011
Expanded Timing Diagrams
FIGURE 20. STANDARD VERTICAL TIMING
FIGURE 21. NON-STANDARD VERTICAL TIMING
EL1881
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September 15, 2011
Applications Information
Video In
Figure 24 shows a “Simplified Block Diagram” on page 11.
An AC-coupled video signal is input to Video In pin 2 via
,
C
1
nominally 0.1µF. Clamp charge current will prevent the
signal on pin 2 from going any more negative than Sync Tip
Ref, about 1.5V. This charge current is nominally about 1mA.
A clamp discharge current of about 10µA is always
attempting to discharge C
1
to Sync Tip Ref, thus charge is
lost between sync pulses that must be replaced during sync
pulses. The droop voltage that will occur can be calculated
from It = CV, where V is the droop voltage, I is the discharge
current, t is the time between sync pulses
(sync period - sync tip width), and C is C
1
.
An NTSC video signal has a horizontal frequency of
15.73kHz, and a sync tip width of 4.7µs. This gives a period
of 63.6µs and a time t = 58.9µs. The droop voltage will then
be V = 5.9mV. This is < 2% of a nominal sync tip amplitude
of 286mV. The charge represented by this droop is replaced
in a time given by t = CV/I, where I = clamp charge current =
1mA. Here t = 590ns, about 12% of the sync pulse width of
4.7µs. It is important to choose C
1
large enough so that the
droop voltage does not approach the switching threshold of
the internal comparator.
Fixed Gain Buffer
The clamped video signal then passes to the fixed gain
buffer which places the sync slice level at the equivalent
level of 70mV above sync tip. The output of this buffer is
presented to the comparator, along with the slice reference.
The comparator output is level shifted and buffered to TTL
levels, and sent out as Composite Sync to pin 1.
Burst
A low-going Burst pulse follows each rising edge of sync,
and lasts approximately 3.5µs for an R
SET
of 681kΩ.
Vertical Sync
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
FIGURE 22. STANDARD VERTICAL TIMING
Expanded Timing Diagrams (Continued)
EL1881

EL1881CS

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC VIDEO SYNC SEPARATOR 8-SOIC
Lifecycle:
New from this manufacturer.
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