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74AUP1T58GS,132

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 15 of 20
NXP Semiconductors
74AUP1T58
Low-power configurable gate with voltage-level translator
Fig 17. Package outline SOT1115 (XSON6)
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm
max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95
0.55 0.3
0.40
0.35
0.32
A
(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
A
1
b
0.20
0.15
0.12
DEee
1
L
0.35
0.30
0.27
L
1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)
(2)
e
1
e
1
e
L
L
1
b
321
6 5 4
(6×)
(2)
A
1
A
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 16 of 20
NXP Semiconductors
74AUP1T58
Low-power configurable gate with voltage-level translator
Fig 18. Package outline SOT1202 (XSON6)
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm
max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95
0.55 0.35
0.40
0.35
0.32
A
(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
A
1
b
0.20
0.15
0.12
DEee
1
L
0.35
0.30
0.27
L
1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)
(2)
e
1
e
1
e
L
b
123
L
1
6 5 4
(6×)
(2)
A
A
1
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 17 of 20
NXP Semiconductors
74AUP1T58
Low-power configurable gate with voltage-level translator
14. Abbreviations
15. Revision history
Table 12. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AUP1T58 v.5 20120815 Product data sheet - 74AUP1T58 v.4
Modifications:
• Package outline drawing of SOT886 (Figure 15) modified.
74AUP1T58 v.4 20111128 Product data sheet - 74AUP1T58 v.3
74AUP1T58 v.3 20101018 Product data sheet - 74AUP1T58 v.2
74AUP1T58 v.2 20090929 Product data sheet - 74AUP1T58 v.1
74AUP1T58 v.1 20080306 Product data sheet - -
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74AUP1T58GS,132

Mfr. #:
Buy 74AUP1T58GS,132
Manufacturer:
Nexperia
Description:
Logic Gates CONFIG 4.6 V 20 mA
Lifecycle:
New from this manufacturer.
Delivery:
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