CY7C53120E4-40AXI Datasheet CY7C53120E4-40AXI, CY7C53120E2-10SXI, CY7C53120E4-40SXI | P13-P15

CY7C53150, CY7C53120

Document Number: 38-10001 Rev. *J Page 13 of 19

Figure 10. Differential Receiver Input Hysteresis Voltage Measurement Waveforms

-1

Neuron Chip's

Internal

Comparator

Voltage

Time

V(CP0)

V(CP1)

V(CP0)-V(CP1)

Vcm

Vtrip+

Vtrip-

Common-Mode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2

Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]

CY7C53150, CY7C53120

Document Number: 38-10001 Rev. *J Page 14 of 19

Ordering Code Definitions

Ordering Information

[23]

Part Number

Flash

(KB)

ROM

(KB)

Firmware

Version

Max Input

Clock

(MHz)

Package

Name

Package Type

CY7C53150-20AXI 0.5 0 N/A 20

[24]

A64SA 64-pin TQFP

CY7C53150-20AXIT 0.5 0 N/A 20

[24]

A64SA 64-pin TQFP – Tape and Reel

CY7C53120E2-10SXI

[25]

2 10 6 10 S32.45 32-pin SOIC

CY7C53120E4-40SXI

[26]

4 12 13 40 S32.45 32-pin SOIC

CY7C53120E4-40SXIT 4 12 13 40 S32.45 32-pin SOIC – Tape and Reel

CY7C53120E4-40AXI

[26]

4 12 13 40 A44 44-pin TQFP

Notes

23. All parts contain 2 KB of SRAM.

24. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later.

25. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware.

26. CY7C53120E4 requires upgraded LonBuilder® and NodeBuilder® software.

CY7C53150, CY7C53120

Document Number: 38-10001 Rev. *J Page 15 of 19

Package Diagrams

Figure 11. 44-pin TQFP (10 × 10 × 1.4 mm) Package Outline, 51-85064

Figure 12. 64-pin TQFP (14 × 14 × 1.4 mm) Package Outline, 51-85046

51-85064 *F

51-85046 *F

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

CY7C53120E4-40AXI

Mfr. #:

Buy CY7C53120E4-40AXI

Manufacturer:

Cypress Semiconductor

Description:

Network Controller & Processor ICs Neuron Chip Integ ROM IND

Lifecycle:

New from this manufacturer.

Delivery:

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CY7C53120E4-40AXI

CY7C53120E4-40AXI

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