© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 0
1 Publication Order Number:
NB3L202K/D
NB3L202K
2.5 V, 3.3 V Differential 1:2
HCSL Fanout Buffer
Description
The NB3L202K is a differential 1:2 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
Features
Maximum Input Clock Frequency > 350 MHz
2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
2 HCSL Outputs
DB200H Compliant
Individual OE Control Pin for Each Output
100 ps Max Output−to−Output Skew Performance
1 ns Typical Propagation Delay
500 ps Typical Rise and Fall Times
80 fs Maximum Additive RMS Phase Jitter
−40°C to +85°C Ambient Operating Temperature
QFN 16−pin Package, 3 mm x 3 mm
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
PCI Express
FBDIMM
Mobile Computing
Networking
Gigabit Ethernet
MARKING
DIAGRAM
www.
onsemi.com
See detailed ordering and shipping information page 13 of this
data sheet.
ORDERING INFORMATION
NB3L202K = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
QFN16
3x3
CASE 485AE
NB3L
202K
ALYWG
G
1
1
NB3L202K
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2
Figure 1. Simplified Block Diagram
Figure 2. 16−Pin QFN Pinout
(Top View)
NB3L202K
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3
Table 1. PIN DESCRIPTION
Pin Number Pin Name I/O Description
1 GND Power Ground
2 CLK_IN I, DIF Differential True input
3 CLK_IN# I, DIF Differential Complementary input
4 VDD Power Core power supply
5 GND_O Power Ground for outputs
6 DIF_1# O, DIF 0.7 V Differential Complementary Output
7 DIF_1 O, DIF 0.7 V Differential True Output
8 VDD_O Power Power supply for outputs
9 GND Power Ground
10 IREF I A precision resistor is attached to this pin to set the differential output current.
Use R
REF
= 475 W, 1% for 100 W trace, with 50 W termination.
Use R
REF
= 412 W, 1% for 85 W trace, with 43 W termination.
11 OE0#
I, SE
LVTTL / LVCMOS active low input for enabling output DIF_0/0#. 0 enables outputs,
1 disables outputs. Internal pull down.
12 OE1#
I, SE
LVTTL / LVCMOS active low input for enabling output DIF_1/1#. 0 enables outputs,
1 disables outputs. Internal pull down.
13 VDD_O Power Power supply for outputs
14 DIF_0 O, DIF 0.7 V Differential True Output
15 DIF_0# O, DIF 0.7 V Differential Complementary Output
16 GND_O Power Ground for outputs
EP Exposed
Pad
Thermal The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electri-
cally and thermally connected to GND on the PC board.

NB3L202KMNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:2 HCSL FANOUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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