MAX8731A
SMBus Level 2 Battery Charger
with Remote Sense
______________________________________________________________________________________ 19
where R
Pack
is the total resistance in the battery pack,
R
Board
is the board resistance in series with the battery
charge path, t
CV0
is the constant-voltage charge time
without remote sense, and t
CVRS
is the constant-volt-
age charge time with remote sense.
The MAX8731A includes a safety feature, which limits
the charge voltage when FBS_ or the selector is dis-
connected. The MAX8731A guarantees that CSIN does
not regulate more than 250mV above the selected
charging voltage. This also limits the extent to which
remote sense can cancel charge-path impedance.
Input Current Measurement
Use IINP to monitor the system-input current sensed
across CSSP and CSSN. The voltage at IINP is propor-
tional to the input current by the equation:
V
IINP
= I
INPUT
x RS1 x G
IINP
x R8
where I
INPUT
is the DC current supplied by the AC
adapter, G
IINP
is the transconductance of IINP (3mA/V
typ), and R8 is the resistor connected between IINP
and ground. Typically, IINP has a 0 to 3.5V output volt-
age range. Leave IINP open if not used.
LDO Regulator
An integrated low-dropout (LDO) linear regulator pro-
vides a 5.4V supply derived from DCIN, and delivers over
30mA of load current. The LDO powers the gate drivers
of the n-channel MOSFETs. See the MOSFET Drivers
section. LDO has a minimum current limit of 35mA. This
allows the MAX8731A to work with 87nC of total gate
charge (both high-side and low-side MOSFETs). Bypass
LDO to PGND with a 1µF or greater ceramic capacitor.
AC Adapter Detection
The MAX8731A includes a hysteretic comparator that
detects the presence of an AC power adapter. When
ACIN is greater than 2.048V, the open-drain ACOK out-
put becomes high impedance. Connect 10kΩ pullup
resistance between LDO and ACOK. Use a resistive
voltage-divider from the adapter’s output to the ACIN
pin to set the appropriate detection threshold. Select
the resistive voltage-divider not to exceed the 6V
absolute maximum rating of ACIN.
V
DD
Supply
The V
DD
input provides power to the SMBus interface.
Connect V
DD
to LDO, or apply an external supply to
V
DD
to keep the SMBus interface active while the sup-
ply to DCIN is removed. When V
DD
is biased the inter-
nal registers are maintained. Bypass V
DD
to GND with
a 0.1µF or greater ceramic capacitor.
Operating Conditions
The MAX8731A has the following operating states:
Adapter Present: When DCIN is greater than 7.5V,
the adapter is considered to be present. In this con-
dition, both the LDO and REF function properly and
battery charging is allowed:
a) Charging: The total MAX8731A quiescent current
when charging is 1mA (max) plus the current required
to drive the MOSFETs.
b) Not Charging: To disable charging, set either
ChargeCurrent() or ChargeVoltage() to zero. When the
adapter is present and charging is disabled, the total
adapter quiescent current is less than 1mA and the
total battery quiescent current is less than 5µA.
Adapter Absent (Power Fail): When V
CSSP
is less
than V
CSIN
+ 10mV, the MAX8731A is in the power-
fail state, since the DC-DC converter is in dropout.
The charger does not attempt to charge in the
power-fail state. Typically, this occurs when the
adapter is absent. When the adapter is absent, the
total MAX8731A quiescent battery current is less
than 1µA (max).
•V
DD
Undervoltage (POR): When V
DD
is less than
2.5V, the V
DD
supply is in an undervoltage state and
the internal registers are in their POR state. The
SMBus interface does not respond to commands.
When V
DD
rises above 2.5V, the MAX8731A is in a
power-on reset state. Charging does not occur until
the ChargeVoltage() and ChargeCurrent() com-
mands are sent. When V
DD
is greater than 2.5V,
SMBus registers are preserved.
The MAX8731A allows charging under the following
conditions:
1) DCIN > 7.5V, LDO > 4V, REF > 3.1V
2) V
CSSP
> V
CSIN
+ 210mV (15mV falling threshold)
3) V
DD
> 2.5V
MAX8731A
SMBus Level 2 Battery Charger
with Remote Sense
20 ______________________________________________________________________________________
S
a) WRITE-WORD FORMAT
W ACK ACK ACK P
COMMAND
BYTE
LOW DATA
BYTE
HIGH DATA
BYTE
SLAVE
ADDRESS
ACK
7 BITS 8 BITS1b
MSB LSB MSB LSB
8 BITS
MSB LSB
8 BITS
MSB LSB0
1b
0
1b
0
1b
0
1b
0
PRESET TO
0b0001001
ChargerMode() = 0x12
ChargeCurrent() = 0x14
ChargeVoltage() = 0x15
AlarmWarning() = 0x16
InputCurrent() = 0x3F
D7 D0 D15 D8
S
b) READ-WORD FORMAT
W ACK ACK NACK P
COMMAND
BYTE
LOW DATA
BYTE
HIGH DATA
BYTE
SLAVE
ADDRESS
SACK
7 BITS 8 BITS1b
MSB LSB
SLAVE
ADDRESS
7 BITS
MSB LSBMSB LSB
8 BITS
MSB LSB
8 BITS
MSB LSB0
1b
0
R ACK
1b
1
1b
0
1b
0
1b
0
1b
1
Preset to
0b0001001
PRESET TO
0b0001001
ChargerSpecInfo() = 0x11
ChargerStatus() = 0x13
D7 D0 D15 D8
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 3. SMBus Write-Word and Read-Word Protocols
SMBus Interface
The MAX8731A receives control inputs from the SMBus
interface. The MAX8731A uses a simplified subset of
the commands documented in System Management
Bus Specification V1.1, which can be downloaded from
www.smbus.org. The MAX8731A uses the SMBus
Read-Word and Write-Word protocols (Figure 3) to
communicate with the smart battery. The MAX8731A
performs only as an SMBus slave device with address
0b0001001_ (0x12) and does not initiate communica-
tion on the bus. In addition, the MAX8731A has two
identification (ID) registers (0xFE): a 16-bit device ID
register and a 16-bit manufacturer ID register (0xFF).
The data (SDA) and clock (SCL) pins have Schmitt-trig-
ger inputs that can accommodate slow edges. Choose
pullup resistors (10kΩ) for SDA and SCL to achieve rise
times according to the SMBus specifications.
Communication starts when the master signals a
START condition, which is a high-to-low transition on
SDA, while SCL is high. When the master has finished
communicating, the master issues a STOP condition,
which is a low-to-high transition on SDA, while SCL is
high. The bus is then free for another transmission.
Figures 4 and 5 show the timing diagram for signals on
the SMBus interface. The address byte, command
byte, and data bytes are transmitted between the
START and STOP conditions. The SDA state changes
only while SCL is low, except for the START and STOP
conditions. Data is transmitted in 8-bit bytes and is
sampled on the rising edge of SCL. Nine clock cycles
are required to transfer each byte in or out of the
MAX8731A because either the master or the slave
acknowledges the receipt of the correct byte during the
ninth clock cycle. The MAX8731A supports the charger
commands as described in Table 4.
MAX8731A
SMBus Level 2 Battery Charger
with Remote Sense
______________________________________________________________________________________ 21
SMBCLK
AB CD
E
FG H
I
J
K
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
HD:DAT
t
SU:STO
t
BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
L
M
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
SMBCLK
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
AB CD
E
FG H
I
J
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
K
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
Figure 4. SMBus Write Timing
Figure 5. SMBus Read Timing

MAX8731AETI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Battery Management SMBus Level 2 Battery Charger
Lifecycle:
New from this manufacturer.
Delivery:
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