9DBV0841AKILF Datasheet 9DBV0841AKLF, 9DBV0841AKILF, 9DBV0841AKLFT | P7-P9

APRIL 28, 2016 7 8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS

9DBV0841 DATASHEET

Electrical Characteristics–Low Power HCSL Outputs

Electrical Characteristics–Current Consumption

TA = T

AMB,

Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

dV/dt Scope averaging on, fast setting 1.7 2.8 4

V/ns

1,2,3

dV/dt Scope averaging on, slow setting 1.1 2.1 3.2

V/ns

1,2,3

Slew rate matchin

dV/dt Slew rate matchin

, Scope avera

on 6.2 20

1,2,4

Voltage High V

HIGH

660 789 850 7

Voltage Low V

LOW

-150 38 150 7

Max Voltage Vmax 803 1150 7

Min Voltage Vmin -300 15 7

Crossing Voltage (abs) Vcross_abs Scope averaging off 250 417 550 mV 1,5

Crossing Voltage (var)

-Vcross Scope averaging off 13 140 mV 1,6

Measured from differential waveform

Guaranteed by design and characterization, not 100% tested in production.

Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

absolute) allowed. The intent is to limit Vcross induced modulation by setting

-Vcross to be smaller than Vcross absolute.

At default SMBus settings.

Slew rate

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

Measurement on single ended signal using

absolute value. (Scope averaging off)

TA = T

AMB,

Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

DDA

VDDA+VDDR, PLL Mode, @100MHz 10.6 15 mA 1

VDD, All outputs active @100MHz 6.1 10 mA 1

DDO

VDDO, All outputs active @100MHz 30.7 35 mA 1

DDAPD

VDDA+VDDR, PLL Mode, @100MHz 0.58 1 mA 1, 2

DDPD

VDD, Outputs Low/Low 0.81 2 mA 1, 2

DDOPD

VDDO,Outputs Low/Low 0.00 0.01 mA 1, 2

Guaranteed by design and characterization, not 100% tested in production.

Input clock stopped.

Operating Supply Current

Powerdown Current

8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS 8 APRIL 28, 2016

9DBV0841 DATASHEET

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

Electrical Characteristics–Phase Jitter Parameters

TA = T

AMB,

Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

-3dB point in Hi

h BW Mode 2 2.7 4 MHz 1,5

-3dB point in Low BW Mode 1 1.4 2 MHz 1,5

PLL Jitter Peaking t

JPEAK

Peak Pass band Gain 1.1 2 dB 1

Duty Cycle t

Measured differentially, PLL Mode 45 50.1 55 % 1

Duty Cycle Distortion t

DCD

Measured differentially, Bypass Mode @100MHz -1 0.03 1 % 1,3

dBYP

Bypass Mode, V

= 50% 2800 3625 4500 ps 1

dPLL

PLL Mode V

= 50% -100 -4 100 ps 1,4

Skew, Output to Output t

sk3

= 50% 39 50 ps 1,4

PLL mode 14 50 ps 1,2

Additive Jitter in Bypass Mode 0.10 25 ps 1,2

Guaranteed by desi

n and characterization, not 100% tested in production.

Measured from differential waveform

Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

All outputs at default slew rate

The MIN/TYP/MAX values of each BW settin

track each other, i.e., Low BW MAX will never occur with Hi BW MIN.

PLL Bandwidth BW

Skew, Input to Output

Jitter, Cycle to cycle t

jcyc-cyc

TA = T

AMB,

Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX

INDUSTRY

LIMIT UNITS Notes

jphPCIeG1

PCIe Gen 1 24 32 86 ps (p-p)

1,2,3,

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.5 0.8 3

(rms)

1,2,3,

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

1.7 2.3

3.1

(rms)

1,2,3,

jphPCIeG3

PCIe Gen 3

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.4 0.6

(rms)

1,2,3,

jphSGMII

125MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

2.0 NA

(rms)

1,6

jphPCIeG1

PCIe Gen 1 0.6 2.6 N/A ps (p-p)

1,2,3,

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.1 0.3 N/A

(rms)

1,2,3,

4,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.14 0.2 N/A

(rms)

1,2,3,

jphPCIeG3

PCIe Gen 3

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.00 0.1 N/A

(rms)

1,2,3,

jphSGMII

125MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

0.27 N/A

(rms)

1,6

Guaranteed by design and characterization, not 100% tested in production.

For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

Driven by 9FGV0841/9FGL0841 or equivalent

Driven by Rohde&Schartz SMA100

Phase Jitter, PLL Mode

jphPCIeG2

Additive Phase Jitter,

Bypass Mode

jphPCIeG2

See http://www.pcisig.com for complete specs

Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

APRIL 28, 2016 9 8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS

9DBV0841 DATASHEET

General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

Note: SMBus Address is Latched on SADR pin.

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X

(H)

was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

X Byte

ACK

Byte N + X - 1

ACK

PstoP bit

Index Block Read Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

RT Repeat starT

Slave Address

RD ReaD

ACK

Data Byte Count=X

ACK

X Byte

Beginning Byte N

ACK

Byte N + X - 1

N Not acknowledge

PstoP bit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

9DBV0841AKILF

Mfr. #:

Buy 9DBV0841AKILF

Manufacturer:

IDT

Description:

Clock Buffer VERY LOW POWER PCIE GEN1-2-3 BUFFER

Lifecycle:

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9DBV0841AKILF

9DBV0841AKILF

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