FDMC9430L-F085 Dual N-Channel Logic Level PowerTrench
®
MOSFET
©2016 Semiconductor Components Industries, LLC.
August-2017, Rev. 2
Publication Order Number:
FDMC9430L-F085/D
1
FDMC9430L-F085
Dual N-Channel Logic Level PowerTrench
®
MOSFET
40 V, 12 A, 8.2 mΩ
Features
Typical R
DS(on)
= 6.3 mΩ at V
GS
= 10V, I
D
= 12 A
Typical Q
g(tot)
= 15 nC at V
GS
= 10V, I
D
= 12 A
UIS Capability
RoHS Compliant
Qualified to AEC Q101
Applications
Battery Protection
Load Switching
Point of Load
MOSFET Maximum Ratings T
J
= 25°C unless otherwise noted.
Symbol Parameter Ratings Units
V
DSS
Drain-to-Source Voltage 40 V
V
GS
Gate-to-Source Voltage ±12 V
I
D
Drain Current - Continuous (V
GS
=10) (Note 1) T
C
= 25°C 12
A
Pulsed Drain Current T
C
= 25°C See Figure 4
E
AS
Single Pulse Avalanche Energy (Note 2) 21.6 mJ
P
D
Power Dissipation 11.4 W
Derate Above 25
o
C0.1W/
o
C
T
J
, T
STG
Operating and Storage Temperature -55 to + 150
o
C
R
θJC
Thermal Resistance, Junction to Case 13
o
C/W
R
θJA
Maximum Thermal Resistance, Junction to Ambient (Note 3) 65
o
C/W
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDMC9430L
FDMC9430L-F085
Power 33 13” 12mm 3000 units
Notes:
1: Current is limited by bondwire configuration.
2: Starting T
J
= 25°C, L = 0.3mH, I
AS
= 12A, V
DD
= 40V during inductor charging and V
DD
= 0V during time in avalanche.
3: R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
mounting surface of the drain pins. R
θJC
is guaranteed by design, while R
θJA
is determined by the board design. The maximum rating
presented here is based on mounting on a 1 in
2
pad of 2oz copper.
D1
D2
S1
G1
S2
G2
Power 33
Pin 1
S1S1
S2S2
G1
S1
S1
S1
4
3
2
18
7
6
5
Bottom Drain1 Contact
Bottom Drain2 Contact
Q2
Q1
G2
S2
S2
S2
