LT3797
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High Side PMOS Disconnect Switch Selection
A PMOS with a minimum V
GS(TH)
of –1V to –2V is rec-
ommended for the high side disconnect switch in most
LT3797
applications to improve the PWM dimming ratio
and protect the LED array from excessive heating during
fault conditions. The PMOS BV
DSS
rating must be higher
than the open-LED regulation voltage set by the FBH pin.
The maximum continuous drain current I
D(MAX)
rating
should be higher than the maximum LED current.
Input Capacitor Selection
The input capacitor C
IN
supplies the AC ripple current to
the power inductor of the converter and must be placed
and sized according to the transient current requirements.
The switching frequency, output current and tolerable input
voltage ripple are key inputs to estimating the required
capacitor value. The X5R or X7R type ceramic capacitors
are usually good choices since they have small variation
with temperature and DC bias. Typically, the boost or SEPIC
converter requires a lower value input capacitor than the
buck mode or buck-boost mode converter, due to the fact
that its inductor is in series with the input, and the input
current waveform is continuous. The input capacitor value
can be estimated based on the inductor ripple I
L
(refer to
Inductor Selection section), the switching frequency, and
the acceptable input voltage ripple V
IN
on C
IN
. C
IN
value
of the boost and SEPIC converter can be calculated by:
C
IN
= 0.125
I
L
V
IN
f
C
IN
value of the buck mode and buck-boost mode LED
driver can be calculated by:
C
IN
=I
LED
V
LED
V
IN(MIN)
V
LED
( )
V
IN(MIN)
2
V
IN
f
Output Capacitor Selection
The output filter capacitors should be sized to attenuate
the LED current ripple. Use of X5R or X7R type ceramic
capacitors is recommended. To achieve the same LED
ripple current, the required filter capacitor is smaller in the
buck mode applications than that in the boost, buck-boost
mode and SEPIC applications. This is due to the fact that,
in the buck converter, the inductor is in series with the
output and the ripple current flowing through the output
capacitor is continuous. Lower operating frequencies will
require proportionately higher capacitor values.
The DC Coupling Capacitor Selection for
SEPIC LED Driver
The DC voltage rating of the DC coupling capacitor, C
DC
,
connected between the primary and secondary inductors
should be larger than the maximum input voltage:
V
CDC
> V
IN(MAX)
C
DC
has nearly a rectangular current waveform in CCM.
During the switch off-time, the current through C
DC
is I
VIN
,
while approximately –I
LED
flows during the on-time. The
C
DC
voltage ripple causes distortions on the primary and
secondary inductor current waveforms. The C
DC
should
be sized to limit its voltage ripple. The power loss on the
C
DC
ESR reduces the LED driver efficiency. Therefore, the
sufficient low ESR ceramic capacitors should be selected.
The X5R or X7R ceramic capacitor is recommended for C
DC
.
Integrated INTV
CC
Power Supply
The LT3797 includes an internal switch mode DC/DC con-
verter to generate a regulated 7.5V INTV
CC
power supply
to power the NMOS gate drivers of the three channels
(I
DRIVE
). This INTV
CC
power supply can also be used to
drive external circuits (I
EXT
). This INTV
CC
power supply
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has two major advantages over the traditional internal
LDO regulators. It is able to generate 7.5V INTV
CC
voltage
from a V
IN
voltage as low as 2.5V, allowing the LT3797 to
drive high threshold MOSFETs in the low V
IN
applications.
It is also able to deliver large current from a V
IN
voltage
as high as 40V without overheating the package, due to
its high efficiency (over 70% at full load). This integrated
DC/DC converter requires three external components (C
VCC
,
C
BOOST
and L
PWR
) for operation, as shown in Figure 1.
Select these three components based on the following
guidelines:
• C
VCC
is a 10μF/10V ceramic capacitor used to bypass
INTV
CC
to GND immediately adjacent to the pins.
• C
BOOST
is a 0.1μF/10V ceramic capacitor connected
between the BOOST pin and the SW1 pin.
• Selecta47µHinductorwiththesaturationcurrentrat
-
ing of 0.6A or greater and RMS current rating of 0.4A
or greater for L
PWR
.
The INTV
CC
power supply has an output current limit func-
tion to protect itself from excessive electrical and thermal
stress. Figure 9 shows the INTV
CC
output limit (I
INTVCC_LMT
)
vs V
IN
and switching frequency. Make sure the sum of the
I
DRIVE
and I
EXT
is always lower than the I
INTVCC_LMT
across
the whole V
IN
range of the application circuit:
I
DRIVE
+ I
EXT
< I
INTVCC_LMT
where:
I
DRIVE
= (Q
G_CH1
+ Q
G_CH2
+ Q
G_CH3
)•f
SW
Q
G_CH1-3
is the total gate charge of the NMOS of the three
channels at V
GS
= 0V to 7.5V.
V
IN
(V)
0
INTV
CC
CURRENT LIMIT I
INTVCC_LMT
(mA)
150
200
250
3739 F09
100
50
125
175
225
75
25
0
3
6 9 12 15 18 21 24 27 30 33 36 39
100kHz
200kHz
300kHz
400kHz
500kHz
600kHz
>900kHz
700kHz800kHz
Figure 9. INTV
CC
Current Limit vs V
IN
, f
SW
Board Layout
The high speed operation of the LT3797 demands careful
attention to board layout and component placement. The
exposed pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the exposed pad and the ground
planes of the board. For the LT3797 to deliver its full output
power, it is imperative that a good thermal path be pro
-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
copper planes with as much area as possible.
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R
PGND
V
IN
C
1615 17 19
53
EXPOSED PAD GND
20 21 22 23 24 25 26
5152 50 49 48 47 46 45 44 43 42 41
33
35
36
37
38
40
C
8
7
6
5
4
3
2
1
32
31
30
28
27
9
10
11
12
14
R
R C
C
C
R
SW_SEN1
RT
SGND
VC2
VC3
SS3
SS2
3797 F10
VC1
SS1
SENSEN1
SENSEP1
SENSEP2
SENSEN2
INTV
CC
V
IN
INTV
CC
C
C
C
PGND
SGND
SGND
SGND
C
R
R
SW_SEN2
R
SW_SEN3
C
C
SENSEP3
SENSEN3
Figure 10. Decoupling Capacitors and Ground Separation
Due to the highly compact integration of the three switching
channels within the LT3797, careful consideration must
be given to possible noise coupling between channels.
To reduce noise coupling, the compensation network
components connected to the VC1-3 pins and the DC
control signal components connected to the SS1-3, RT,
EN/UVLO, and CTRL1-3 pins must be connected to signal
ground (SGND). The signal ground (SGND) and power
ground (PGND) connection should only occur at the
LT3797 exposed GND pad (pin 53). Further, board traces
for high impedance signals such as FBH1-3 and VC1-3
should be kept to the shortest length possible to avoid
unwanted noise pick up. Also, the decoupling capacitors
that connect V
IN
to PGND and INTV
CC
to PGND should be
physically located close to their respective pins. Finally, for
high voltage and/or high current applications, an effective
approach to attenuate possible switch noise coupling into
each channel’s control loop is to add a small footprint size
0.1µF ceramic capacitor between each SENSEP pin and
the corresponding SENSEN pin. When used, these noise
filtering capacitors should be physically located near
their respective pins. Figure 10 provides an example of a
PCB layout of the decoupling capacitors, compensation
networks and ground separation.
To reduce electromagnetic interference (EMI) and high
frequency resonance problems, proper layout of the LT3797
LED driver power stage is essential, especially the power
paths with high di/dt. Figures 11-14 show the simplified
power stage circuits of boost, buck mode, buck-boost
mode and SEPIC topologies with the high di/dt loops high
-
lighted. The high di/dt loops of different topologies should
be kept as tight as possible to reduce inductive ringing.
Figures15-16 shows the examples of the high di/dt loop
layout of the different topologies shown in Figures 11-14.

LT3797IUKG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
LED Lighting Drivers 3x Out LED Drvr Cntr
Lifecycle:
New from this manufacturer.
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