REV. C
AD9764
–15–
I
OUTFS
and R
LOAD
can be selected as long as the positive compli-
ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the Ana-
log Output section of this data sheet. For optimum INL perfor-
mance, the single-ended, buffered voltage output configuration
is suggested.
AD9764
I
OUTA
I
OUTB
21
50V
25V
50V
V
OUTA
= 0 TO +0.5V
I
OUTFS
= 20mA
22
Figure 36. 0 V to +0.5 V Unbuffered Voltage Output
SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 37 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the
AD9764 output current. U1 maintains I
OUTA
(or I
OUTB
) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the Ana-
log Output section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distor-
tion performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar
output voltage and its full-scale output voltage is simply the
product of R
FB
and I
OUTFS
. The full-scale output should be set
within U1’s voltage output swing capabilities by scaling I
OUTFS
and/or R
FB
. An improvement in ac distortion performance may
result with a reduced I
OUTFS
since the signal current U1 will be
required to sink will be subsequently reduced.
AD9764
22
I
OUTA
I
OUTB
21
C
OPT
200V
U1
V
OUT
= I
OUTFS
3 R
FB
I
OUTFS
= 10mA
R
FB
200V
Figure 37. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing and supply bypassing and grounding.
Figures 42–47 illustrate the recommended printed circuit board
ground, power and signal plane layouts that are implemented on
the AD9764 evaluation board.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9764 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physi-
cally possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close as physically as possible.
For those applications requiring a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 38. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
100mF
ELECT.
10-22mF
TANT.
0.1mF
CER.
TTL/CMOS
LOGIC
CIRCUITS
+5V OR +3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
Figure 38. Differential LC Filter for Single +5 V or +3 V
Applications
Maintaining low noise on power supplies and ground is critical
to obtain optimum results from the AD9764. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding current trans-
port, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.
All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some “free” capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous volt-
age drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, strip line techniques with proper termination resistors
should be considered. The necessity and value of this resistor
will be dependent upon the logic family used.
For a more detailed discussion of the implementation and con-
struction of high speed, mixed signal printed circuit boards,
refer to Analog Devices’ application notes AN-280 and AN-333.
REV. C
AD9764
–16–
MULTITONE PERFORMANCE CONSIDERATIONS AND
CHARACTERIZATION
The frequency domain performance of high speed DACs has
traditionally been characterized by analyzing the spectral output
of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave
at a particular output frequency and update rate. Although this
characterization data is useful, it is often insufficient to reflect a
DAC’s performance for a reconstructed multitone or spread-
spectrum waveform. In fact, evaluating a DAC’s spectral
performance using a full-scale, single tone at the highest specified
frequency (i.e., f
H
) of a bandlimited waveform is typically
indicative of a DAC’s “worst-case” performance for that given
waveform. In the time domain, this full-scale sine wave repre-
sents the lowest peak-to-rms ratio or crest factor (i.e., V
PEAK
/V
rms) that this bandlimited signal will encounter.
MAGNITUDE – dBm
FREQUENCY – MHz
–10
–70
–110
2.19 2.812.25 2.31 2.38 2.44 2.50 2.56 2.63 2.69 2.75
–20
–60
–80
–100
–40
–50
–90
–30
Figure 39a. Multitone Spectral Plot
TIME
1.0000
0.8000
–1.0000
VOLTS
–0.2000
–0.4000
–0.6000
–0.8000
0.2000
0.0000
0.4000
0.6000
Figure 39b. Time Domain “Snapshot” of the Multitone
Waveform
However, the inherent nature of a multitone, spread spectrum,
or QAM waveform, in which the spectral energy of the wave-
form is spread over a designated bandwidth, will result in a
higher peak-to-rms ratio when compared to the case of a simple
sine wave. As the reconstructed waveform’s peak-to-average
ratio increases, an increasing amount of the signal energy is
concentrated around the DAC’s midscale value. Figure 39a is
just one example of a bandlimited multitone vector (i.e., eight
tones) centered around one-half the Nyquist bandwidth (i.e.,
f
CLOCK
/4). This particular multitone vector, has a peak-to-rms
ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of
3 dB. A “snapshot” of this reconstructed multitone vector in the
time domain as shown in Figure 39b reveals the higher signal
content around the midscale value. As a result, a DAC’s
“small-scale” dynamic and static linearity becomes increas-
ingly critical in obtaining low intermodulation distortion and
maintaining sufficient carrier-to-noise ratios for a given modula-
tion scheme.
A DAC’s small-scale linearity performance is also an important
consideration in applications where additive dynamic range is
required for gain control purposes or “predistortion” signal
conditioning. For instance, a DAC with sufficient dynamic
range can be used to provide additional gain control of its
reconstructed signal. In fact, the gain can be controlled in
6 dB increments by simply performing a shift left or right on the
DAC’s digital input word. Other applications may intentionally
predistort a DAC’s digital input signal to compensate for
nonlinearities associated with the subsequent analog compo-
nents in the signal chain. For example, the signal compression
associated with a power amplifier can be compensated for by
predistorting the DAC’s digital input with the inverse nonlinear
transfer function of the power amplifier. In either case, the
DAC’s performance at reduced signal levels should be carefully
evaluated.
A full-scale single tone will induce all of the dynamic and static
nonlinearities present in a DAC that contribute to its distortion
and hence SFDR performance. Referring to Figure 3, as the
frequency of this reconstructed full-scale, single-tone waveform
increases, the dynamic nonlinearities of any DAC (i.e., AD9764)
tend to dominate thus contributing to the rolloff in its SFDR
performance. However, unlike most DACs, which employ an R-2R
ladder for the lower bit current segmentation, the AD9764 (as
well as other TxDAC members) exhibits an improvement in
distortion performance as the amplitude of a single tone is re-
duced from its full-scale level. This improvement in distortion
performance at reduced signal levels is evident if one compares
the SFDR performance vs. frequency at different amplitudes
(i.e., 0 dBFS, –6 dBFS and –12 dBFS) and sample rates as
shown in Figures 4 through 7. Maintaining decent “small-scale”
linearity across the full span of a DAC transfer function is also
critical in maintaining excellent multitone performance.
Although characterizing a DAC’s multitone performance tends
to be application-specific, much insight into the potential per-
formance of a DAC can also be gained by evaluating the DAC’s
swept power (i.e., amplitude) performance for single, dual and
multitone test vectors at different clock rates and carrier frequen-
cies. The DAC is evaluated at different clock rates when recon-
structing a specific waveform whose amplitude is decreased in
3 dB increments from full-scale (i.e., 0 dBFS). For each specific
waveform, a graph showing the SFDR (over Nyquist) perfor-
mance vs. amplitude can be generated at the different tested
clock rates as shown in Figures 9–11. Note that the carrier(s)-
to-clock ratio remains constant in each figure. In each case, an
improvement in SFDR performance is seen as the amplitude is
reduced from 0 dBFS to approximately –9.0 dBFS.
A multitone test vector may consist of several equal amplitude,
spaced carriers each representative of a channel within a defined
bandwidth as shown in Figure 39a. In many cases, one or more
tones are removed so the intermodulation distortion performance
REV. C
AD9764
–17–
of the DAC can be evaluated. Nonlinearities associated with the
DAC will create spurious tones of which some may fall back into
the “empty” channel thus limiting a channel’s carrier-to-noise
ratio. Other spurious components falling outside the band of
interest may also be important, depending on the system’s spectral
mask and filtering requirements.
This particular test vector was centered around one-half the
Nyquist bandwidth (i.e., f
CLOCK
/4) with a passband of f
CLOCK
/16.
Centering the tones at a much lower region (i.e., f
CLOCK
/10)
would lead to an improvement in performance while centering
the tones at a higher region (i.e., f
CLOCK
/2.5) would result in a
degradation in performance. Figure 40a shows the SFDR vs.
amplitude at different sample rates up to the Nyquist frequency
while Figure 40b shows the SFDR vs. amplitude within the
passband of the test vector. In assessing a DAC’s multitone
performance, it is also recommended that several units be tested
under exactly the same conditions to determine any performance
variability.
A
OUT
– dBFS
SFDR – dBc
80
50
–20 –15 0
–10 –5
70
60
10 MSPS
100 MSPS
20 MSPS
50 MSPS
40
30
75
65
55
45
35
Figure 40a. Multitone SFDR vs. A
OUT
(Up to Nyquist)
SFDR – dBc
50
70
60
40
75
65
55
45
80
10 MSPS
20 MSPS
50 MSPS
100 MSPS
A
OUT
– dBFS
–20 –15 0–10 –5
Figure 40b. Multitone SFDR vs. A
OUT
(Within Multitone
Passband)
AD9764 EVALUATION BOARD
General Description
The AD9764-EB is an evaluation board for the AD9764 14-bit
DAC converter. Careful attention to layout and circuit design,
combined with a prototyping area, allows the user to easily and
effectively evaluate the AD9764 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9764
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators with the
onboard option to add a resistor network for proper load termi-
nation. Provisions are also made to operate the AD9764 with
either the internal or external reference or to exercise the power-
down feature.
Refer to the application note AN-420, Using the AD9760/AD9764/
AD9764-EB Evaluation Board for a thorough description and
operating instructions for the AD9764 evaluation board.

AD9764ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 14-Bit 100 MSPS
Lifecycle:
New from this manufacturer.
Delivery:
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