6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA)..
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71321)
t
BAA
BUSY Access Time from Address
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20 ns
t
BA C
BUSY Access Time from Chip Enable
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20 ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
50
____
50 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
35
____
35 ns
t
AP S
Arbitration Priority Set-up Time
(2 )
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
25
____
35 ns
BUSY INPUT TIMING (For SLAVE 71421)
t
WB
Write to BUSY Input
(4 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
40
____
50 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
30
____
35 ns
2691 tbl 10a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71321)
t
BAA
BUSY Access Time from Address
____
20
____
30 ns
t
BDA
BUSY Disable Time from Address
____
20
____
30 ns
t
BA C
BUSY Access Time from Chip Enable
____
20
____
30 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
30 ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
60
____
80 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
35
____
55 ns
t
AP S
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
35
____
50 ns
BUSY INPUT TIMING (For SLAVE 71421)
t
WB
Write to BUSY Input
(4 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1 )
____
60
____
80 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
35
____
55 ns
2691 tbl 10b