8
LT1490/LT1491
Supply Voltage
The positive supply pin of the LT1490/LT1491 should be
bypassed with a small capacitor (about 0.01µF) within an
inch of the pin. When driving heavy loads an additional
4.7µF electrolytic capacitor should be used. When using
split supplies, the same is true for the negative supply pin.
The LT1490/LT1491 are protected against reverse battery
voltages up to 18V. In the event a reverse battery condition
occurs, the supply current is less than 1nA.
The LT1490/LT1491 can be shut down by removing V
+
. In
this condition the input bias current is less than 0.1nA,
even if the inputs are 44V above the negative supply.
When operating the LT1490/LT1491 on total supplies of
30V or more, the supply must not be brought up faster
than 1µs. This is especially true if low ESR bypass capaci-
tors are used. A series RLC circuit is formed from the
supply lead inductance and the bypass capacitor. 5Ω of
resistance in the supply or the bypass capacitor will
dampen the tuned circuit enough to limit the rise time.
Inputs
The LT1490/LT1491 have two input stages, NPN and PNP
(see the Simplified Schematic), resulting in three distinct
operating regions as shown in the Input Bias Current vs
Common Mode typical performance curve.
For input voltages about 0.8V or more below V
+
, the PNP
input stage is active and the input bias current is typically
–4nA. When the input voltage is about 0.5V or less from
V
+
, the NPN input stage is operating and the input bias
current is typically 18nA. Increases in temperature will
cause the voltage at which operation switches from the
PNP stage to the NPN stage to move towards V
+
. The input
offset voltage of the NPN stage is untrimmed and is
typically 600µV.
A Schottky diode in the collector of each NPN transistor of
the NPN input stage allows the LT1490/LT1491 to operate
with either or both of its inputs above V
+
. At about 0.3V
above V
+
the NPN input transistor is fully saturated and the
input bias current is typically 4µA at room temperature.
The input offset voltage is typically 700µV when operating
above V
+
. The LT1490/LT1491 will operate with its inputs
44V above V
–
regardless of V
+
.
The inputs are protected against excursions as much as
22V below V
–
by an internal 1k resistor in series with each
input and a diode from the input to the negative supply.
There is no output phase reversal for inputs up to 22V
below V
–
. There are no clamping diodes between the
inputs and the maximum differential input voltage is 44V.
Output
The output voltage swing of the LT1490/LT1491 is af-
fected by input overdrive as shown in the typical perfor-
mance curves. When monitoring voltages within 100mV
of either rail, gain should be taken to keep the output from
clipping.
The output of the LT1490/LT1491 can be pulled up to 18V
beyond V
+
with less than 1nA of leakage current, provided
that V
+
is less than 0.5V.
The normally reverse-biased substrate diode from the
output to V
–
will cause unlimited currents to flow when the
output is forced below V
–
. If the current is transient and
limited to 100mA, no damage will occur.
The LT1490/LT1491 is internally compensated to drive at
least 200pF of capacitance under any output loading
conditions. A 0.22µF capacitor in series with a 150Ω
resistor between the output and ground will compensate
these amplifiers for larger capacitive loads, up to 10,000pF,
at all output currents.
Distortion
There are two main contributors of distortion in op amps:
output crossover distortion as the output transitions from
sourcing to sinking current and distortion caused by
nonlinear common mode rejection. Of course, if the op
amp is operating inverting there is no common mode
induced distortion. When the LT1490 switches between
input stages there is significant nonlinearity in the CMRR.
Lower load resistance increases the output crossover
distortion, but has no effect on the input stage transition
distortion. For lowest distortion the LT1490/LT1491 should
be operated single supply, with the output always sourc-
ing current and with the input voltage swing between
ground and (V
+
– 0.8V). See the Typical Performance
Characteristics curves.
APPLICATIO S I FOR ATIO
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