MMA6222EG
Sensors
Freescale Semiconductor 15
3.1.1.1 Reset Control (RES_1, RES_0)
A specific series of three write operations involving these two bits will cause the internal digital circuitry to be reset. The state of
the remaining bits in the DEVCTL register do not affect the reset sequence, however any write operation involving this register
in which both RES_1 and RES_0 are cleared will terminate the sequence.
To reset the internal digital circuitry, the following register write operations must be performed in the order shown:
1. Set RES1. RES0 must remain cleared.
2. Set RES1 and RES0.
3. Clear RES1 and set RES0.
RES1 and RES0 are always read as logic ‘0’ values. After reset sequence has been completed DEVCTL register will read 0X00.
It should be noted that after a reset or power-cycle sequence is completed the DEVCTL register reset to the value 0X00.
3.1.1.2 Clear Error (CE)
Setting this bit to a logic ‘1’ state will clear transient error status conditions. It is necessary to either set this bit or perform a device
reset if an error condition has been reported by the device before acceleration data transfer can be resumed. The device reset
condition may be cleared only after device initialization has completed.
Error conditions and classification are described in Section 4.2.
The state of this bit is always read as logic ‘0’.
3.1.1.3 High-Pass Filter Bypass (HPFB)
Setting this bit will remove the high-pass filter from the signal chain within the DSP block. The state of this bit is indicated when
DEVCTL is read. This bit is always cleared following reset.
The state of the high-pass filter is frozen when this bit is at a logic ‘1’ level.
3.1.1.4 Self-Test Control (ST1, ST0)
Bidirectional self-test control is provided through manipulation of these bits. ST1 controls direction while ST0 enables and dis-
ables the self-test circuitry. ST1 and ST0 are always cleared following internal reset. When ST0 is set, the high-pass filter is by-
passed and the values within the high-pass filter are frozen. Both axes are affected simultaneously by the state of these bits. If
the offset monitor is enabled, self-test activation in a single direction should be limited to less than 30 ms.
The state of the ST0 bit is indicated as part of all acceleration results.
3.1.1.5 Y-Axis Signal Inversion Control (YINV)
This control function is provided as a means to verify operation of the two-channel multiplexor which alternately provides X-axis
and Y-axis data to the DSP. An inverter block and multiplexor at the Y-axis input to the DSP are controlled by the YINV bit. Setting
this bit when ST0 is set has the effect of changing the sign of acceleration in the Y-axis. Operation of the YINV bit is illustrated in
Figure 3-1 below. Y-axis inversion may be selected only during self-test; the state of this bit has no effect when ST0 is cleared.
Figure 3-1 Y-Axis Inversion Function
DSP
YINV
ΣΔ
CONVERTER
SINC
FILTER
X
ΣΔ
CONVERTER
Y
SINC
FILTER
ST0
0
1
