SG3525A
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4
ELECTRICAL CHARACTERISTICS (V
CC
= +20 Vdc, T
A
= T
low
to T
high
[Note 3], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (T
J
= +25°C) V
ref
5.00 5.10 5.20 Vdc
Line Regulation (+8.0 V V
CC
+35 V) Reg
line
10 20 mV
Load Regulation (0 mA I
L
20 mA) Reg
load
20 50 mV
Temperature Stability V
ref
/T 20 mV
Total Output Variation Includes Line and Load Regulation over Temperature V
ref
4.95 5.25 Vdc
Short Circuit Current (V
ref
= 0 V, T
J
= +25°C) I
SC
80 100 mA
Output Noise Voltage (10 Hz f 10 kHz, T
J
= +25°C) V
n
40 200 V
rms
Long Term Stability (T
J
= +125°C) (Note 4) S 20 50 mV/khr
OSCILLATOR SECTION (Note 5, unless otherwise noted.)
Initial Accuracy (T
J
= +25°C) ±2.0 ±6.0 %
Frequency Stability with Voltage
(+8.0 V V
CC
+35 V)
f
osc
D
VCC
±1.0 ±2.0 %
Frequency Stability with Temperature
f
osc
D
T
±0.3 %
Minimum Frequency (R
T
= 150 k, C
T
= 0.2 F) f
min
50 Hz
Maximum Frequency (R
T
= 2.0 k, C
T
= 1.0 nF) f
max
400 kHz
Current Mirror (I
RT
= 2.0 mA) 1.7 2.0 2.2 mA
Clock Amplitude 3.0 3.5 V
Clock Width (T
J
= +25°C) 0.3 0.5 1.0 s
Sync Threshold 1.2 2.0 2.8 V
Sync Input Current (Sync Voltage = +3.5 V) 1.0 2.5 mA
ERROR AMPLIFIER SECTION (V
CM
= +5.1 V)
Input Offset Voltage
V
IO
2.0 10 mV
Input Bias Current I
IB
1.0 10 A
Input Offset Current I
IO
1.0 A
DC Open Loop Gain (R
L
10 M) A
VOL
60 75 dB
Low Level Output Voltage V
OL
0.2 0.5 V
High Level Output Voltage V
OH
3.8 5.6 V
Common Mode Rejection Ratio (+1.5 V V
CM
+5.2 V) CMRR 60 75 dB
Power Supply Rejection Ratio (+8.0 V V
CC
+35 V) PSRR 50 60 dB
PWM COMPARATOR SECTION
Minimum Duty Cycle
DC
min
0 %
Maximum Duty Cycle DC
max
45 49 %
Input Threshold, Zero Duty Cycle (Note 5) V
th
0.6 0.9 V
Input Threshold, Maximum Duty Cycle (Note 5) V
th
3.3 3.6 V
Input Bias Current I
IB
0.05 1.0 A
3. T
low
= 0° T
high
= +70°C
4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average
stability from lot to lot.
5. Tested at f
osc
= 40 kHz (R
T
= 3.6 k, C
T
= 0.01 F, R
D
= 0 ).
SG3525A
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5
ELECTRICAL CHARACTERISTICS (continued)
Characteristics Symbol Min Typ Max Unit
SOFT−START SECTION
Soft−Start Current (V
shutdown
= 0 V) 25 50 80 A
Soft−Start Voltage (V
shutdown
= 2.0 V) 0.4 0.6 V
Shutdown Input Current (V
shutdown
= 2.5 V) 0.4 1.0 mA
OUTPUT DRIVERS (Each Output, V
CC
= +20 V)
Output Low Level
(I
sink
= 20 mA)
(I
sink
= 100 mA)
V
OL
0.2
1.0
0.4
2.0
V
Output High Level
(I
source
= 20 mA)
(I
source
= 100 mA)
V
OH
18
17
19
18
V
Under Voltage Lockout (V8 and V9 = High) V
UL
6.0 7.0 8.0 V
Collector Leakage, V
C
= +35 V (Note 6) I
C(leak)
200 A
Rise Time (C
L
= 1.0 nF, T
J
= 25°C) t
r
100 600 ns
Fall Time (C
L
= 1.0 nF, T
J
= 25°C) t
f
50 300 ns
Shutdown Delay (V
DS
= +3.0 V, C
S
= 0, T
J
= +25°C) t
ds
0.2 0.5 s
Supply Current (V
CC
= +35 V) I
CC
14 20 mA
6. Applies to SG3525A only, due to polarity of output pulses.
Reference Regulator
Flip/
Flop
PWM
+
E/A
DUT
V
ref
Clock
16
4
0.1
3
6
7
5
Deadtime
100
0.001
Comp
10k
9
0.01
1
2
1
2
3
1
2
3
3
2
1
3
+
1 = V
IO
2 = 1(+)
3 = 1(−)
0.1
0.009
1.5k
1.0k
3.0k
PWM
ADJ.
Sync
RT
Ramp
50A
5.0k
5.0k
15
13
11
V
C
Out A
0.1
0.1
1.0k, 1.0W
(2)
14
Out B
GND
12
8
Softstart
5.0F
10
2.0k
Shutdown
V
ref
+
O
s
c
i
l
l
a
t
o
r
V/I Meter
V
CC
A
1
2
B
Figure 2. Lab Test Fixture
SG3525A
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6
R
T
, TIMING RESISTOR (k )
Figure 3. Oscillator Charge Time versus R
T
Figure 4. Oscillator Discharge Time versus R
D
Figure 5. Error Amplifier Open Loop
Frequency Response
Figure 6. Output Saturation
Characteristics
2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000
CHARGE TIME (s)
6
57
R
D
*
C
T
R
T
* R
D
= 0
0.2 0.5 1.0 2.0 5.0 10 20 50 100 200
DISCHARGE TIME (s)
, DEAD TIME RESISTOR ()
D
R
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
1
2
9
C
P
R
Z
f, FREQUENCY (Hz)
, VOLTAGE GAIN (dB)
VOL
+
A
R
Z
= 20 k
V
ref
R
T
C
T
Sync
Discharge
GND
16
6
5
3
7
12
Q2
Q1
Q6 Q9
2.0k
2.0k 14k
Q10
Q11
5.0pF
400A
23k
Q4
Q7
1.0k
Q12
Q13
3.0k
250
4
Blanking
To Output
Ramp
To PWM
Q14
25k
7.4k
Q5 Q8
Q3
OSC Output
1.0k
15
Q3
V
CC
9
30
Compensation
1
2
Q4
Q1 Q2
Inverting
Input
5.8V
100A
To PWM
Comparator
200A
Noninverting
Input
Figure 7. Oscillator Schematic
0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0
I
O,
OUTPUT SOURCE OR SINK CURRENT (A)
, SATURATION VOLTAGE (V)
sat
V
Sink Sat, (V
OL
)
Source Sat, (V
C
−V
OH
)
V
CC
= +20 V
T
J
= +25°C
Figure 8. Error Amplifier Schematic
200
100
50
20
10
5.0
2.0
500
400
300
200
100
0
100
80
60
40
20
0
−20
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0

SG3525ADWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 8-35V PWM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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