LTC1099
3
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
U
LTC1099AI/LTC1099I LTC1099AC/LTC1099C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
V
IH
High Level Input Voltage All Digital Inputs, V
CC
= 5.25V ● 2.0 2.0 V
V
IL
Low Level Input Voltage All Digital Inputs, V
CC
= 4.75V ● 0.8 0.0001 0.8 V
I
IH
High Level Input Current V
IH
= 5V; CS, RD, Mode ● 0.0001 1 1 µA
V
IH
= 5V; WR ● 0.0005 3 0.0005 3 µA
I
IL
Low Level Input Current V
IL
= 0V; All Digital Inputs ● –0.0001 –1 –0.0001 –1 µA
V
OH
High Level Output Voltage DB0-DB7, OFL, INT; V
CC
= 4.75V
I
OUT
= 360µA ● 2.4 4.0 2.4 4.0 V
I
OUT
=10µA 4.7 4.7 V
V
OL
Low Level Output Voltage DB0-DB7, OFL, INT, RDY; V
CC
= 4.75V
I
OUT
=1.6mA ● 0.4 0.4 V
I
OZ
Hi-Z Output Leakage DB0-DB7, RDY; V
OUT
= 5V ● 0.1 3 0.1 3 µA
DB0-DB7, RDY; V
OUT
= 0V ● –0.1 –3 –0.1 –3 µA
I
SOURCE
Output Source Current DB0-DB7, OFL, INT; V
OUT
= 0V ● –11 –6 –11 –7 mA
I
SINK
Output Sink Current DB0-DB7, OFL, INT, RDY; V
OUT
= 5V ● 14 7 14 9 mA
I
CC
Supply Current CS = WR = RD = V
CC
● 11 20 11 15 mA
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
CC
= 5V, REF
+
= 5V, REF
–
= 0V and T
A
= T
MIN
to T
MAX
unless otherwise noted.
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. V
CC
= 5V, REF
+
= 5V, REF
–
= 0V and T
A
= T
MIN
to T
MAX
unless otherwise noted.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltages are with respect to GND (Pin 10) unless otherwise
noted.
AC CHARACTERISTICS
Note 3: Total unadjusted error includes offset, gain, linearity and hold step
errors.
Note 4: Reference input voltage range is guaranteed but is not tested.
LTC1099AI/LTC1099I LTC1099AC/LTC1099C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RD Mode (Figure 2) Pin 7 = GND
t
CRD
Conversion Time T
A
= 25°C 2.2 2.5 2.8 2.2 2.5 2.8 µs
● 5.0 3.75 µs
t
RDY
Delay From CS↓ to RDY↓ C
L
= 100pF 70 70 ns
t
ACC0
Delay From RD↓ to Output Data Valid C
L
= 100pF t
CRD
+ 35 t
CRD
+ 35 ns
t
INTH
Delay From RD↑ to INT↑ C
L
= 100pF 70 70 ns
t
1H
, t
0H
Delay From RD↑ to Hi-Z State on Outputs Test Circuit Figure 1 70 70 ns
t
P
Delay Time Between Conversions 700 700 ns
t
ACC2
Delay Time From RD↓ to Output Data Valid 70 70 ns
WR/RD Mode (Figures 3 and 4) Pin 7 = V
CC
t
CWR
Conversion Time T
A
= 25°C 2.2 2.5 2.8 2.2 2.5 2.8 µs
● 5.0 3.75 µs
t
ACC0
Delay Time From WR↓ to Output Data Valid C
L
= 100pF t
CWR
+ 40 t
CWR
+ 40 ns
t
ACC2
Delay From RD↓ to Output Data Valid C
L
= 100pF 70 70 ns
t
INTH
Delay From RD↑ to INT↑ C
L
= 100pF 70 70 ns
t
IHWR
Delay From WR↓ to INT↑ C
L
= 100pF 240 240 ns
t
1H
, t
0H
Delay From RD↑ to Hi-Z State on Outputs Test Circuit Figure 1 70 70 ns
t
P
Delay Time Between Conversions 700 700 ns
t
WR
Minimum WR Pulse Width 55 55 ns
