LTC7138
19
7138f
For more information www.linear.com/LTC7138
applicaTions inForMaTion
The undervoltage and overvoltage lockout requirements
on V
IN
can be satisfied with a resistive divider from V
IN
to
the RUN and OVLO pins (refer to Figure 9). Choose R3 +
R4 + R5 = 2.5M to minimize the loading on V
IN
. Calculate
R3, R4 and R5 as follows:
R5=
V
IN_OV(RISING)
= 33.6k
R4=
1.21V •2.5MΩ
V
IN_UV(RISING)
–R5= 67.2k
Since specific resistor values in the megohm range are
generally less available, it may be necessary to scale R3,
R4, and R5 to a standard value of R3. For this example,
choose R3 = 2.2M and scale R4 and R5 by 2.2M/2.4M.
Then, R4 = 61.6k and R5 = 30.8k. Choose standard values
of R3 = 2.2M, R4 = 62k, and R5 = 30.9k. Note that the fall
-
ing thresholds for both UVLO and OVLO will be 10% less
than the rising thresholds, or 27V and 81V respectively.
The I
SET
pin should be left open in this example to select
maximum peak current (610mA). Figure 11 shows a
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC7138. Check the following in your layout:
1. Large switched currents flow in the power switch, catch
diode, and input capacitor. The loop formed by these
components should be as small as possible. A ground
plane is recommended to minimize ground impedance.
2. Connect the (+) terminal of the input capacitor, C
IN
, as
close as possible to the V
IN
pin. This capacitor provides
the AC current into the internal power MOSFET.
3. Keep the switching node, SW, away from all sensitive
small signal nodes. The rapid transitions on the switching
node can couple to high impedance nodes, in particular
V
FB
, and create increased output ripple.
7138 F11
V
FB
I
SET
FBO
SW
ANODE
V
IN
RUN
2.2M
267k
196k
1µF
33µF
V
OUT
12V
V
IN
62k
30.9k
OVLO
V
PRG2
LTC7138
SS
V
PRG1
GND
Figure 11. 36V to 72V Input to 12V Output, 400mA Regulator
V
FB
ANODE
I
SET
SW
V
IN
RUN
R3
R1
D1
R2
C
IN
C
OUT
V
IN
R4
R
ISET
R5
OVLO
V
PRG1
SS
V
PRG2
LTC7138
GND
FBO
C
SS
7138 F12
C
OUT
V
OUT
V
IN
GND
GND
R3
R
ISET
C
SS
R5
VIAS TO GROUND PLANE
VIAS TO INPUT SUPPLY (V
IN
)
VIAS TO OUTPUT SUPPLY (V
OUT
)
OUTLINE OF LOCAL GROUND PLANE
R4
R1R2
L1
C
IN
D1
Figure 12. Example PCB Layout
