MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
_______________________________________________________________________________________
5
12
0
0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
2
10
MAX500-01
V
OUT
(V)
I
SINK
(mA)
8
6
4
2610
8
4
14
16
V
SS
= -5V
R
O
≅ 200Ω
V
SS
= 0V
10
-6
SUPPLY CURRENT
vs. TEMPERATURE
-4
6
MAX500-02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
0
-2
4
2
8
12
-55 125
25-25 0 7550 100
I
DD
I
SS
1.5
-2.0
ZERO-CODE ERROR
vs. TEMPERATURE
-1.5
1.0
MAX500-03
TEMPERATURE (°C)
ZERO-CODE ERROR (mV)
0.0
-1.0
0.5
-0.5
2.0
-55 12525-25 0 7550 100
V
SS
= -5V
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
____________________________Typical Operating Characteristics (continued)
_______________Detailed Description
The MAX500 has four matched voltage-output digital-to-
analog converters (DACs). The DACs are “inverted”
R-2R ladder networks which convert 8 digital bits into
equivalent analog output voltages in proportion to the
applied reference voltage(s). Two DACs in the MAX500
have a separate reference input while the other two
DACs share one reference input. A simplified circuit
diagram of one of the four DACs is provided in Figure 1.
V
REF
Input
The voltage at the V
REF
pins (pins 4, 12, and 13) sets
the full-scale output of the DAC. The input impedance
of the V
REF
inputs is code dependent. The lowest
value, approximately 11kΩ (5.5kΩ for V
REF
A/B), occurs
when the input code is 01010101. The maximum value
of infinity occurs when the input code is 00000000.
Because the input resistance at V
REF
is code depen-
dent, the DAC’s reference sources should have an out-
put impedance of no more than 20Ω (no more than
10Ω for V
REF
A/B). The input capacitance at V
REF
is
also code dependent and typically varies from 15pF to
35pF (30pF to 70pF for V
REF
A/B). V
OUT
A, V
OUT
B,
V
OUT
C, and V
OUT
D can be represented by a digitally
programmable voltage source as:
V
OUT
= N
b
x V
REF
/ 256
where N
b
is the numeric value of the DAC’s binary
input code.
Output Buffer Amplifiers
All voltage outputs are internally buffered by precision
unity-gain followers, which slew at greater than 3V/µs.
When driving 2kΩ in parallel with 100pF with a full-scale
transition (0V to +10V or +10V to 0V), the output settles
to ±1/2LSB in less than 4µs. The buffers will also drive
2kΩ in parallel with 500pF to 10V levels without oscilla-
tion. Typical dynamic response and settling perfor-
mance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is
shown in Figure 4. Input common-mode range to
AGND is provided by a PMOS input structure. The out-
put circuitry incorporates a pull-down circuit to actively
drive V
OUT
to within +15mV of the negative supply
(V
SS
). The buffer circuitry allows each DAC output to
R
RR
2R
2R 2R 2R 2R
V
REF
AGND
V
OUT
DB0 DB5 DB6 DB7
DB0
DB5
DB6
DB7
…
…
…
Figure 1. Simplified DAC Circuit Diagram
