MK2771-16RLF

DATASHEET
VCXO AND SET-TOP CLOCK SOURCE MK2771-16
IDT™
VCXO AND SET-TOP CLOCK SOURCE 1
MK2771-16 REV G 051310
Description
The MK2771-16 is a low-cost, low-jitter, high-performance
VCXO and clock synthesizer designed for set-top boxes.
The on-chip Voltage Controlled Crystal Oscillator accepts a
0 to 3 V input voltage to cause the output clocks to vary by
±100 ppm. Using IDT’s patented VCXO and analog
Phase-Locked Loop (PLL) techniques, the device uses an
inexpensive 13.5 MHz pullable crystal input to produce
multiple output clocks including two selectable processor
clocks, a selectable audio clock, two communications
clocks, a 13.5 MHz clock, and three 27 MHz clocks. All
clocks are frequency locked to the 27 MHz output (and to
each other) with zero ppm error, so any output can be used
as the VCXO output.
Features
Packaged in 28-pin QSOP
RoHS 5 (green) or RoHS 6 (green and lead free)
compliant package
On-chip patented VCXO with pull range of 200 ppm
VCXO tuning voltage of 0 to 3 V
Processor frequencies include 16.66, 20, 25, 32, 40, and
50 MHz
Audio clocks support 32 kHz, 44.1 kHz, 48 kHz, and 96
kHz sampling rates
Zero ppm synthesis error in all clocks (all exactly track 27
MHz VCXO)
Uses an inexpensive 13.5 MHz pullable crystal
Full CMOS output swings with 25 mA output drive
capability at TTL levels
Advanced, low-power, sub-micron CMOS process
5 V operating voltage with 3.3 V capable I/O
Block Diagram
ACLK
Voltage
Controlled
Crystal
Oscillator
X1
X2
13.5 MHz
pullable
crystal
27.000 MHz
PCLK
PLL Clock
Synthesis
Circuitry
13.500 MHz
CCLK2
CCLK1
VDDIO
GND
VDD5
VIN
CS1, CS0
PS1, PS0
AS2:0
3
x2
PLL
divide
by 2
2
3
2
Optional crystal capacitors.
3
6
MK2771-16
VCXO AND SET-TOP CLOCK SOURCE VCXO AND SYNTHESIZER
IDT™
VCXO AND SET-TOP CLOCK SOURCE 2
MK2771-16 REV G 051310
Pin Assignment
Processor Clock Select Table (MHz)
Audio Clock Table (MHz)
Communications Clock Table (MHz)
0 = connect directly to ground
1 = connect directly to VDDIO
M = leave floating or unconnected
18
7
17
8
16
9
15
VDDIO
10
VDD5
11
CS1
12
AS2
13
GND
14
GND
GND
GND
27M
PCLK
CCLK1
13.5M
CCLK2
PS1
22
21
20
19
ACLK
VDD5
5
6
VDD5
VIN
27M
24
23
GND
3
4
GND
X1
27M
26
25
CS0
1
2
PS0
X2
AS0
28
27
AS1
28-pin QSOP
PS1 PS0 PCLK
00 50
0 1 16.667
M0 25
M1 32
10 40
11 20
AS2 AS1 AS0 ACLK
000 8.192
0 0 1 11.2896
0 1 0 12.288
0 1 1 5.6448
1 0 0 18.432
1 0 1 16.9344
1 1 0 49.152
1 1 1 21.576
CS1 CS0 CCLK1 CCLK2
0 0 Low 33.333
0 1 Low 24.576
1 0 11.0592 18.432
1 1 11.0592 3.6864
MK2771-16
VCXO AND SET-TOP CLOCK SOURCE VCXO AND SYNTHESIZER
IDT™
VCXO AND SET-TOP CLOCK SOURCE 3
MK2771-16 REV G 051310
Pin Descriptions
Pin
Number
Pin
Name
Pin Type Pin Description
1 PS0 Input Processor clock select 0. Selects PCLK frequency. See table
above. Internal pull-up resistor.
2 X2 XO Crystal connection. Connect to a 13.5 MHz fundamental mode
pullable crystal.
3, 10, 11 GND Power Connect to ground.
4 X1 XI Crystal connection. Connect to a 13.5 MHz fundamental mode
pullable crystal.
5, 8, 22 VDD5 Power Connect to +5 V.
6 VIN Input Voltage input to VCXO. Zero to 3 V signal which controls the
frequency of the VCXO.
7 VDDIO Power Connect to +3.3 V or +5 V. Amplitude of inputs and outputs will
match this.
9 CS1 Input Communications clock select pin 1. Selects CCLK 1 and 2 per
table above. Internal pull-up.
12 PCLK Output Processor clock output. Determined by status of PS1, PS0.
13 CCLK2 Output Communications clock output 2 determined by status of CS1,
CS0 per table above.
14 ACLK Output Audio clock output. Determined by status of AS2:0 per table
above.
15 13.5M Output 13.5 MHz VCXO clock output.
16 PS1 Tri-level Input Processor Clock Select 1. Selects PCLK frequency. See table
above. Self-biased to M.
17 CCLK1 Output Communications clock output 1 determined by status of CS1,
CS0 per table above.
18, 23, 25 27M Output 27 MHz VCXO clock output.
19, 20, 24 GND Power Connect to ground.
21 AS2 Input Audio clock select 2. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
26 CS0 Input Communications clock select pin 0. Selects CCLK 1 and 2 per
table above. Internal pull-up.
27 AS0 Input Audio clock select 0. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
28 AS1 Input Audio clock select 1. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.

MK2771-16RLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner VCXO AND SET-TOP CLOCK SOURCE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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