MAX159BCUA+T Datasheet MAX157BEUA+T, MAX157AEUA+T, MAX157ACPA | P7-P9

MAX157/MAX159

+2.7V, Low-Power, 2-Channel,

108ksps, Serial 10-Bit ADCs in 8-Pin µMAX

_______________________________________________________________________________________ 7

Detailed Description

The MAX157/MAX159 analog-to-digital converters

(ADCs) use a successive-approximation conversion

(SAR) technique and on-chip track/hold (T/H) structure

to convert an analog signal to a serial, 10-bit digital out-

put data stream.

This flexible serial interface provides easy interface to

microprocessors (µPs). Figure 2 shows a simplified

functional diagram of the internal architecture for both

the MAX157 (2 channels, single-ended) and the

MAX159 (1 channel, pseudo-differential).

Single-Ended (MAX157) and Pseudo-

Differential (MAX159) Analog Inputs

The sampling architecture of the ADC’s analog com-

parator is illustrated in the equivalent input circuit in

Figure 3. In single-ended mode (MAX157), both chan-

nels CH0 and CH1 are referred to GND and can be

connected to two different signal sources. Following the

power-on reset, the ADC is set to convert CH0. After

CH0 has been converted, CH1 will be converted, and

the conversions will continue to alternate between

channels. Channel switching is performed by toggling

the CS/SHDN pin. Conversions can be performed on

the same channel by toggling CS/SHDN twice between

conversions. If only one channel is required, CH0 and

CH1 may be connected together; however the output

data will still contain the channel identification bit

(before the MSB).

For the MAX159, the input channels form a single differ-

ential channel pair (CH+, CH-). This configuration is

pseudo-differential to the effect that only the signal at

IN+ is sampled. The return side IN- must remain stable

within ±0.5LSB (±0.1LSB for optimum results) with

respect to GND during a conversion. To accomplish

this, connect a 0.1µF capacitor from IN- to GND.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor C

HOLD

. The

acquisition interval spans from when CS/SHDN falls to

the falling edge of the second clock cycle (external

clock mode) or from when CS/SHDN falls to the first

falling edge of SCLK (internal clock mode). At the end

of the acquisition interval, the T/H switch opens, retain-

ing charge on C

HOLD

as a sample of the signal at IN+.

The conversion interval begins with the input multiplex-

er switching C

HOLD

from the positive input (IN+) to the

negative input (IN-). This unbalances node ZERO at the

comparator’s positive input.

6k C

DOUT

a) HIGH-Z TO V

, V

TO V

, AND V

TO HIGH-Z

DOUT

GNDGND

b) HIGH-Z TO V

, V

TO V

, AND V

TO HIGH-Z

Figure 1. Load Circuits for Enable and Disable Time

Pin Description

NAME FUNCTION

1 V

Positive Supply Voltage, +2.7V to +5.25V

2 CH0 (CH+) Analog Input, MAX157: Single-Ended (CH0); MAX159: Differential (CH+).

3 CH1 (CH-) Analog Input, MAX157: Single-Ended (CH1); MAX159: Differential (CH-).

4 GND Analog and Digital Ground

8 SCLK Serial Clock Input. DOUT changes on the falling edge of SCLK.

7 DOUT

Serial Data Output. Data changes state at SCLK’s falling edge. High impedance when CS/SHDN is high.

CS/SHDN

Active-Low Chip-Select Input, Active-High Shutdown Input. Pulling CS/SHDN high puts chip into

shutdown with a maximum current of 5µA.

5 REF

External Reference Voltage Input. Sets analog voltage range. Bypass with a 100nF capacitor close to the

part.

MAX157/MAX159

+2.7V, Low-Power, 2-Channel,

108ksps, Serial 10-Bit ADCs in 8-Pin µMAX

8 _______________________________________________________________________________________

The capacitive digital-to-analog converter (DAC)

adjusts during the remainder of the conversion cycle

to restore node ZERO to 0V within the limits of 10-bit

resolution. This action is equivalent to transferring a

16pF · [(V

+) - (V

-)] charge from C

HOLD

to the bina-

ry-weighted capacitive DAC, which in turn forms a digi-

tal representation of the analog input signal.

Track/Hold

The ADC’s T/H stage enters its tracking mode on the

falling edge of CS/SHDN. For the MAX157 (single-

ended inputs), IN- is connected to GND and the con-

verter samples the positive (“+”) input. For the MAX159

(pseudo-differential inputs), IN- connects to the nega-

tive input (“-”), and the difference of [(V

+) - (V

-)] is

sampled. At the end of the conversion, the positive

input connects back to IN+ and C

HOLD

charges to the

input signal.

The time required for the T/H stage to acquire an input

signal is a function of how fast its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens and more time must be

allowed between conversions. The acquisition time,

ACQ

, is the maximum time the device takes to acquire

the signal, and is also the minimum time required for

the signal to be acquired. Calculate this with the follow-

ing equation:

ACQ

= 7(R

+ R

where R

is the source impedance of the input signal,

(9kΩ) is the input resistance, and C

(16pF) is the

input capacitance of the ADC. Source impedances

below 4kΩ have no significant impact on the AC perfor-

mance of the MAX157/MAX159.

Higher source impedances can be used if a 0.01µF

capacitor is connected to the individual analog inputs.

Together with the input impedance, this capacitor forms

an RC filter, limiting the ADC’s signal bandwidth.

Input Bandwidth

The MAX157/MAX159 T/H stage offers both a 2.25MHz

small-signal and a 1MHz full-power bandwidth, which

makes it possible to use the parts for digitizing high-

speed transients and measuring periodic signals with

bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid high-fre-

quency signals being aliased into the frequency band

of interest, anti-alias filtering is recommended. Most

aliasing problems can be fixed easily with an external

resistor and a capacitor. However, if DC precision is

required, it is usually best to choose a continuous

or switched-capacitor filter, such as the MAX7410/

MAX7414 (Figure 4). Their Butterworth characteristic

generally provides the best compromise (with regard to

rolloff and attenuation) in filter configurations, is easy to

design, and provides a maximally flat passband re-

sponse.

Analog Input Protection

Internal protection diodes, which clamp the analog

input to V

and GND, allow each input channel to

swing within GND - 300mV to V

+ 300mV without

damage. However, for accurate conversions both

inputs must not exceed V

+ 50mV or be less than

GND - 50mV.

If an off-channel analog input voltage exceeds the

supplies, limit the input current to 4mA.

MAX157

MAX159

10+2 BIT

SAR

ADC

SCLK

IN OUT

ANALOG

INPUT

MUX

(2 CHANNEL)

CH0

(CH+)

CH1

(CH-)

REF

( ) ARE FOR MAX159

T/H

CONTROL

LOGIC

SCLK

CS/SHDN

INTERNAL

CLOCK

OUTPUT

DOUT

Figure 2. MAX157/MAX159 Simplified Functional Diagram

CH0

(CH+)

CH1

(CH-)

GND

SWITCH

TRACK

T/H

HOLD

CAPACITIVE DAC

CONTROL

LOGIC

REF

ZERO

TO SAR

( ) ARE FOR MAX159

COMPARATOR

–

HOLD

16pF

SINGLE-ENDED MODE: CHO, CH1 = IN+; GND = IN-

DIFFERENTIAL MODE: CH+ = IN+; CH- = IN-

INPUT

MUX

Figure 3. Analog Input Channel Structure

Selecting Clock Mode

To start the conversion process on the MAX157/

MAX159, pull CS/SHDN low. At CS/SHDN’s falling

edge, the part wakes up, the internal T/H enters track

mode, and a conversion begins. In addition, the state of

SCLK at CS/SHDN’s falling edge selects internal (SCLK

= high) or external (SCLK = low) clock mode.

Internal Clock (f

SCLK

< 100kHz or f

SCLK

> 2.17MHz)

In internal clock mode, the MAX157/MAX159 run from

an internal, laser-trimmed oscillator to within 20% of the

2MHz specified clock rate. This releases the system

microprocessor from running the SAR conversion clock

and allows the conversion results to be read back at the

processor’s convenience, at any clock rate from 0 to

5MHz. Operating the MAX157/MAX159 in internal clock

mode is necessary for serial interfaces operating with

clock frequencies lower than 100kHz or greater than

2.17MHz. Select internal clock mode (Figure 5) by hold-

ing SCLK high during a high/low transition of CS/SHDN.

The first SCLK falling edge samples the data and initi-

ates a conversion using the integrated on-chip oscilla-

tor. After the conversion, the oscillator shuts off and

DOUT goes high, signaling the end of conversion

(EOC). Data can then be read out with SCLK.

External Clock (f

SCLK

= 100kHz to 2.17MHz)

External clock mode (Figure 6) is selected by transition-

ing CS/SHDN from high to low while SCLK is low. The

external clock signal not only shifts data out, but also

drives the analog-to-digital conversion. The input is

sampled and conversion begins on the falling edge of

the second clock pulse. Conversion must be completed

within 140µs to prevent degradation in the conversion

results caused by droop on the T/H capacitors. External

clock mode provides the best throughput for clock fre-

quencies between 100kHz and 2.17MHz.

MAX157/MAX159

+2.7V, Low-Power, 2-Channel,

108ksps, Serial 10-Bit ADCs in 8-Pin µMAX

_______________________________________________________________________________________ 9

Figure 4. Analog Input with Anti-Aliasing Filter Structure

DOUT

D7D8MSBCHID11EOC

SAMPLING INSTANT

HIGH-Z

D6 D5 D4 D3 D2 D1 D0 S1 S0

HIGH-Z

SCLK

678 9101112345 1213141516

CONV

WAKE

ACQ

)

POWER

DOWN

ACTIVE ACTIVE

CS/SHDN

Figure 5. Internal Clock Mode Timing

SHDN

OUT

CLK

REF

EXTERNAL

REFERENCE

CS/SHDN

DOUT

µP/µC

MAX7410

MAX7414

CH0

GNDOS GNDCOM

0.01µF

0.1µF

470Ω

0.01µF

CH1

CORNER

= 15kHz

SCLK

MAX157

1.5MHz

CLOCK

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX159BCUA+T

Mfr. #:

Buy MAX159BCUA+T

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 10-Bit 108ksps 5.25V Precision ADC

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MAX159BCUA+T

MAX159BCUA+T

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