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X20C04P-15

P1-P3P4-P6P7-P9P10-P12P13-P15
Obsolete Product
REV 1.0 6/21/00
Characteristics subject to change without notice.
1 of 15
www.xicor.com
4K
X20C04
512 x 8 Bit
Nonvolatile Static RAM
FEATURES
• High reliability
—Endurance: 1,000,000 nonvolatile store
operations
—Retention: 100 years minimum
•Power-on recall
—EEPROM data automatically recalled into
SRAM upon power-up
• Lock out inadvertent store operations
•Low power CMOS
—Standby: 250µA
• Infinite EEPROM array recall, and RAM read and
write cycles
• Compatible with X2004
DESCRIPTION
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electri-
cally erasable PROM (EEPROM). The X20C04 is fabri-
cated with advanced CMOS floating gate technology
to achieve low power and wide power-supply margin.
The X20C04 features the JEDEC approved pinout for
byte-wide memories, compatible with industry stan-
dard RAMs, ROMs, EPROMs, and EEPROMs.
The NOVRAM design allows data to be easily transferred
from RAM to EEPROM (store) and EEPROM to RAM
(recall). The store operation is completed in 5ms or less
and the recall operation is completed in 5µs or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
EEPROM, and a minimum 1,000,000 store operations
to the EEPROM. Data retention is specified to be
greater than 100 years.
BLOCK DIAGRAM
V
CC
Sense
Row
Select
Control
Logic
Column
Select
&
I/OS
EEPROM Array
512 x 8
SRAM
Array
CE
OE
WE
NE
A
3
–A
6
I/O
0
–I/O
7
A
0
–A
2
A
7
–A
8
RECALL
STORE
Obsolete Product
X20C04
Characteristics subject to change without notice.
2 of 15
REV 1.0 6/21/00
www.xicor.com
PIN CONFIGURATION
NE
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
V
CC
WE
NC
A
8
NC
NC
OE
NC
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
X20C04
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
A
6
NC
I/O
0
A
8
NC
NC
NC
OE
NC
CE
I/O
7
I/O
6
NC
4 3 2 1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
X20C04
(Top View)
LCC
PLCC
WE
V
CC
NC
NE
NC
A
7
A
5
A
4
A
3
A
2
A
1
A
0
I/O
5
I/O
3
NC
I/O
2
I/O
1
V
SS
I/O
4
Plastic CERDIP
PIN NAMES
PIN DESCRIPTIONS
Addresses (A
0
–A
8
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
Output Enable (OE
)
The Output Enable input controls the data output buff-
ers and is used to initiate read and recall operations.
Output Enable LOW disables a store operation regard-
less of the state of CE, WE, or NE.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
both the static RAM and stores to the EEPROM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls all accesses to
the EEPROM array (store and recall functions).
DEVICE OPERATION
The CE, OE, WE and NE inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a 2-
line control architecture to eliminate bus contention in a
system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
Symbol Description
A
0
–A
8
Address inputs
I/O
0
–I/O
7
Data input/output
WE
Write enable
CE
Chip enable
OE
Output enable
NE
Nonvolatile enable
V
CC
+5V
V
SS
Ground
NC No connect
Obsolete Product
X20C04
Characteristics subject to change without notice.
3 of 15
REV 1.0 6/21/00
www.xicor.com
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the
X20C04.
Nonvolatile Operations
With NE LOW, recall operation is performed in the
same manner as RAM read operation. A recall opera-
tion causes the entire contents of the EEPROM to be
written into the RAM array. The time required for the
operation to complete is 5µs or less. A store operation
causes the entire contents of the RAM array to be
stored in the nonvolatile EEPROM. The time for the
operation to complete is 5ms or less.
Power-Up Recall
Upon power-up (V
CC
), the X20C04 performs an auto-
matic array recall. When V
CC
minimum is reached, the
recall is initiated, regardless of the state of CE, OE,
WE and NE.
Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvola-
tile memory and the RAM.
–V
CC
Sense—All functions are inhibited when V
CC
is
3.5V.
–A RAM write is required before a Store Cycle is
initiated.
–Write Inhibit—Holding either OE LOW, WE HIGH,
CE HIGH, or NE HIGH during power-up and power-
down will prevent an inadvertent store operation.
– Noise Protection—A combined WE, NE, OE and CE
pulse of less than 20ns will not initiate a Store Cycle.
– Noise Protection—A combined WE, NE, OE and CE
pulse of less than 20ns will not initiate a recall cycle.
SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
P1-P3P4-P6P7-P9P10-P12P13-P15

X20C04P-15

Mfr. #:
Buy X20C04P-15
Manufacturer:
Renesas / Intersil
Description:
IC NVSRAM 4K PARALLEL 28DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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