2002 Oct 24 6
Philips Semiconductors Product specification
600 V CCFL ballast driver IC UBA2070
FUNCTIONAL DESCRIPTION
Start-up state
Initial start-up can be achieved by charging C
VDD
using an
external start-up resistor. The start-up of the circuit is such,
that the MOSFETs T
ls
and T
hs
shall be non-conductive.
The circuit will be reset in the start-up state. If the V
DD
supply reaches the value of V
DD(high)
the circuit starts
oscillating. A DC reset circuit is incorporated in the high
side (hs) driver. Below the lockout voltage at pin FV
DD
the
output voltage (V
GH
− V
SH
) is zero. The voltages at pins
CF and CT are zero during the start-up state.
Oscillation
The internal oscillator is a Voltage Controlled Oscillator
circuit (VCO) which generates a sawtooth waveform
between the high level at pin CF and 0 V (see Fig.4). The
frequency of the sawtooth is determined by C
CF
,
R
IREF
and the voltage at pin CSW. The minimum and
maximum frequencies are determined by C
CF
and R
IREF
.
The minimum to maximum ratio is fixed internally. The
sawtooth frequency is twice the half bridge frequency. The
IC brings the MOSFETs T
hs
and T
ls
alternately into
conduction with a duty factor of 50%.The oscillator starts
oscillating at f
max
. During the first switching cycle the
MOSFET T
ls
is switched on. To charge the bootstrap
capacitor the first conduction time after the start-up state is
made extra long. In all other cases the duty factor at the
start is 50%.
Non-overlap time
The non-overlap time is realized with an Adaptive
Non-Overlap circuit (ANT). By using this circuit, the
application determines the duration of the non-overlap
time (determined by the slope of the half bridge voltage
and detected by the signal across R
ACM
) and makes the
non-overlap time optimum for each frequency (see Fig.4).
The minimum non-overlap time is internally fixed. The
maximum non-overlap time is internally fixed at
approximately 25% of the bridge period time.
Timing circuit
A timing circuit is included (a clock generator) to determine
the maximum ignition time. The ignition time is defined as
1 pulse at pin CT; the lamp has to ignite within the duration
of this pulse. The timer circuit starts operating when a
critical value of the lamp voltage [V
LVS(fail)
] is exceeded.
When the timer is not operating the capacitor at pin CT is
discharged by 1 mA to 0 V.
Ignition state
After the start at f
max
the frequency will decrease due to
charging the capacitor at pin CSW with an internally fixed
current. During this continuous decrease in frequency, the
circuit approaches the resonant frequency of the lamp.
This will cause a high voltage across the lamp, which
ignites the lamp. The ignition voltage of the lamp is
designed to be above the V
LVS(fail)
level. If the lamp voltage
exceeds this voltage level the ignition timer is started (see
Fig.5).
Burn state
If the lamp voltage does not exceed the V
LVS(max)
level the
voltage at pin CSW will continue to increase until the
clamp level at pin CSW is reached. As a consequence the
frequency will decrease until the minimum frequency is
reached. When the frequency reaches its minimum level it
is assumed that the lamp has ignited, the circuit will enter
the burn state and the Average Current Sensor (ACS)
circuit will be enabled (see Fig.5). As soon as the average
voltage across R
sense
(measured at pin CS−) reaches the
reference level at pin CS+, the average current sensor
circuit will take over the control of the lamp current. The
average current through R
sense
is transferred to a voltage
at the voltage controlled oscillator to regulate the
frequency and, as a result, the lamp current.
Lamp failure
DURING IGNITION STATE
If the lamp fails to ignite, the voltage level increases. When
the lamp voltage exceeds the V
LVS(max)
level, the voltage
will be regulated at that level. The ignition timer is started
when the V
LVS(fail)
level is exceeded. If the voltage at
pin LVS is above the V
LVS(fail)
level at the end of the
ignition time the circuit stops oscillation and is forced into
a Power-down state (see Fig.6).Thisstate is terminated by
switching off the V
DD
supply.
DURING BURN STATE
If the lamp fails during normal operation, the voltage
across the lamp will increase and the lamp voltage will
exceed the V
LVS(fail)
level. This forces the circuit to re-enter
the ignition state and results in an attempt to re-ignite the
lamp. If during restart the lamp still fails, the voltage
remains high until the end of the ignition time. At the end
of the ignition time the circuit stops oscillating and enters
the Power-down state (see Fig.7).
