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AD5227BUJZ100-R2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD5227
Rev. B | Page 3 of 16
ELECTRICAL CHARACTERISTICS
10 kΩ, 50 kΩ, 100 kΩ versions: V
DD
= 3 V ± 10% or 5 V ± 10%, V
A
= V
DD
, V
B
= 0 V, −40°C < T
A
< +105°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ
1
Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL R
WB
, A = no connect −0.5 ±0.15 +0.5 LSB
Resistor Integral Nonlinearity
2
R-INL R
WB
, A = no connect −1 ±0.3 +1 LSB
Nominal Resistor Tolerance
3
∆R
AB
/R
AB
−20 +20 %
Resistance Temperature Coefficient (∆R
AB
/R
AB
)/∆T × 10
6
35 ppm/°C
Wiper Resistance R
W
V
DD
= 2.7 V 100 250 Ω
V
DD
= 2.8 V to 5.5 V 50 200 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE
Resolution N 6 Bits
Integral Nonlinearity
3
INL −1 ±0.1 +1 LSB
Differential Nonlinearity
3, 4
DNL −0.5 ±0.1 +0.5 LSB
Voltage Divider Temperature Coefficient (∆V
W
/V
W
)/∆T × 10
6
Midscale 5 ppm/°C
Full-Scale Error V
WFSE
≥+31 steps from midscale −1.2 −0.5 0 LSB
−40°C < T
A
< +60°C,
V
DD
= 2.8 V to 5.5 V
−1 −0.5 0 LSB
Zero-Scale Error V
WZSE
≤−32 steps from midscale 0 0.5 1.2 LSB
−40°C < T
A
< +60°C,
V
DD
= 2.8 V to 5.5 V
0 0.5 1 LSB
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
With respect to GND 0 V
DD
V
Capacitance A, B
6
C
A, B
f = 1 MHz, measured to
GND
140 pF
Capacitance W
6
C
W
f = 1 MHz, measured to
GND
150 pF
Common-Mode Leakage I
CM
V
A
= V
B
= V
W
1 nA
DIGITAL INPUTS (CS, CLK, U/D)
Input Logic High V
IH
2.4 5.5 V
Input Logic Low V
IL
0 0.8 V
Input Current I
I
V
IN
= 0 V or 5 V ±1 μA
Input Capacitance
6
C
I
5 pF
POWER SUPPLIES
Power Supply Range V
DD
2.7 5.5 V
Supply Current I
DD
V
IH
= 5 V or V
IL
= 0 V,
V
DD
= 5 V
0.4 3 μA
Power Dissipation
7
P
DISS
V
IH
= 5 V or V
IL
= 0 V,
V
DD
= 5 V
17 μW
Power Supply Sensitivity PSSR V
DD
= 5 V ± 10% 0.01 0.05 %/%
DYNAMIC CHARACTERISTICS
6,
8,
9
Bandwidth −3 dB BW_10 k R
AB
= 10 kΩ, midscale 460 kHz
BW_50 k R
AB
= 50 kΩ, midscale 100 kHz
BW_100 k R
AB
= 100 kΩ, midscale 50 kHz
Total Harmonic Distortion THD
V
A
= 1 V rms, R
AB
= 10 kΩ,
V
B
= 0 V dc, f = 1 kHz
0.05 %
Adjustment Settling Time t
S
V
A
= 5 V ± 1 LSB error
band, V
B
= 0, measured at
V
W
1 μs
Resistor Noise Voltage e
N_WB
R
WB
= 5 kΩ, f = 1 kHz 14 nV/√Hz
Footnotes on the next page.
AD5227
Rev. B | Page 4 of 16
Parameter Symbol Conditions Min Typ
1
Max Unit
INTERFACE TIMING CHARACTERISTICS (applies to all parts
6, 10
)
Clock Frequency f
CLK
50 MHz
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 10 ns
CS to CLK Setup Time
t
CSS
10 ns
CS
Rise to CLK Hold Time
t
CSH
10 ns
U/D
to Clock Fall Setup Time
t
UDS
10 ns
1
Typicals represent average readings at 25°C, V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
NL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use V
DD
= V.
10
All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
V
DD
= 5 V.
INTERFACE TIMING DIAGRAMS
04419-0-004
CS = LOW
U/D = HIGH
CLK
R
WB
Figure 2. Increment R
WB
04419-0-005
CS = LOW
U/D = 0
CLK
R
WB
Figure 3. Decrement R
WB
04419-0-006
1
0
1
0
1
0
CS
CLK
U/D
R
WB
t
S
t
UDS
t
CL
t
CH
t
CSS
t
CSH
Figure 4. Detailed Timing Diagram (Only R
WB
Decrement Shown)
AD5227
Rev. B | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
V
DD
to GND −0.3 V, +7 V
V
A
, V
B
, V
W
to GND 0 V, V
DD
Digital Input Voltage to GND (CS, CLK, U/D)
0 V, V
DD
Maximum Current
I
WB
, I
WA
Pulsed ±20 mA
I
WB
Continuous (R
WB
≤ 5 kΩ, A open)
1
±1 mA
I
WA
Continuous (R
WA
≤ 5 kΩ, B open)
1
±1 mA
I
AB
Continuous
(R
AB
= 10 kΩ/50 kΩ/100 kΩ)
1
±500 μA/
±100 μA/±50 μA
Operating Temperature Range −40°C to +105°C
Maximum Junction Temperature (T
J
max) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 s – 30 s) 245°C
Thermal Resistance
2
θ
JA
230°C/W
1
Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. V
DD
= 5 V.
2
Package power dissipation = (T
J
max – T
A
) / θ
JA
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD5227BUJZ100-R2

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Buy AD5227BUJZ100-R2
Manufacturer:
Analog Devices Inc.
Description:
Digital Potentiometer ICs IC 6-Bit Up/Down
Lifecycle:
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