Si5018
Rev. 1.3 15
5. Pin Descriptions: Si5018
Figure 10. Si5018 Pin Configuration
Table 8. Si5018 Pin Descriptions
Pin # Pin Name I/O Signal Level Description
1 REXT
External Bias Resistor.
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 kΩ (1%) resis-
tor.
4
5
REFCLK+
REFCLK–
ISee Table2
Differential Reference Clock.
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
6LOLOLVTTL
Loss-of-Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
9
10
DIN+
DIN–
ISee Table2
Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins.
12
13
DOUT–
DOUT+
OCML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
GND
Pad
Connection
15
14
13
12
11
PWRDN/CAL
DOUT+
VDD
DOUT–
VDD
1
2
3
4
5
VDD
GND
REFCLK–
REXT
REFCLK+
20 19 18 17 16
GND
GND
CLKOUT–
CLKOUT+
GND
6 7 8 9 10
LOL
GND
DIN+
DIN–
VDD
