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PL133-97QC

P1-P3P4-P6P7-P9
PL133-97
Low-Power DC to 150MHz 1:9 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 05/22/14 Page 1
FEATURES
1:9 LVCMOS output fanout buffer for DC to 150MHz
8mA Output Drive Strength
Low power consumption for portable applications
Low input-output delay
Output-Output skew less than 250ps
Low Additive Phase Jitter of 60fs RMS
2.5V to 3.3V, ±10% operation
1.8V ± 10% operation up to 67MHz
Operating temperature range from -40°C to 85°C
Available in 16-Pin QFN GREEN/RoHS package
DESCRIPTION
The PL133-97 is an advanced fanout buffer design for
high performance, low-power, small form factor applica-
tions. The PL133-97 accepts a reference clock input from
DC to 150MHz and provides 6 outputs of the same fre-
quency.
The PL133-97 is offered in a QFN-16L 3x3mm package
and it offers the best phase noise, additive jitter perfor-
mance, and lowest power consumption of any comparable
IC.
The PL133-97 outputs can be disabled to a high imped-
ance (tri-state) by pulling low the OE pin. When the OE pin
is high, the outputs are enabled and follow the REF input
signal. When the OE pin is left open, a pull-up resistor on
the chip will default the OE pin to logic 1 so the outputs are
enabled.
CLK8 is a free running output that remains enabled
when the OE pin is pulled low.
BLOCK DIAGRAM AND PACKAGE PINOUT
REF
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
QFN-16L
OE
CLK8
CLK7
CLK9
CLK4
OE
CLK3
GND
CLK8
CLK7
REF
CLK1
VDD
GND
CLK2
CLK6
VDD
GND
CLK5
1 2 3 4
8
7
6
5
12 11 10 9
13
14
15
16
CLK9
PL133-97
Low-Power DC to 150MHz 1:9 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 05/22/14 Page 2
PIN DESCRIPTIONS
Name
QFN-16L
Type
Description
REF
15
I
Input reference frequency.
CLK1
1
O
Buffered clock output
CLK2
4
O
Buffered clock output
CLK3
5
O
Buffered clock output
CLK4
8
O
Buffered clock output
CLK5
9
O
Buffered clock output
CLK6
12
O
Buffered clock output
CLK7
13
O
Buffered clock output
CLK8
14
O
Buffered clock output, free running, does not disable with OE.
CLK9
16
O
Buffered clock output
VDD
2, 11
P
VDD connection
GND
3, 7, 10
P
GND connection
OE
6
I
Output Enable Control Input with 130K Pull-Up
ePad
-
-
Center Pad for Thermal Relief. Connect to GND.
PL133-97
Low-Power DC to 150MHz 1:9 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474 -1000 • www.micrel.com Rev 05/22/14 Page 3
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or “mi-
crostrips” with defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 ohm)
To CMOS Input
Connect a 33 ohm series resistor at each of the output clocks to
enhance the stability of the output signal
50 ohm line
P1-P3P4-P6P7-P9

PL133-97QC

Mfr. #:
Buy PL133-97QC
Manufacturer:
Microchip Technology / Micrel
Description:
Clock Buffer 9-Output CMOS Buffer in QFN Package
Lifecycle:
New from this manufacturer.
Delivery:
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