HTOP01
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Digital Input Low Voltage
Applies to XCLK, SEL, SHDN pins
Supply Current w/SHDN
asserted
Notes
(1) As temperature increases, current into the op amp inputs becomes dominated by leakage current from the input protect
diodes. At 250 C junction temperature, diode leakage current can reach 100nA when the input level is near VDD or VSS. Net
leakage current drops significantly as the input level approaches mid-rail, and is at a minimum when the input level is precisely
midway between VDD and VSS.
Additionally, the diode structures on each input are well matched to each other, and will exhibit nearly identical leakage current
behavior. Consequently, offset current IOS between the two inputs is typically about 1% of the IB level. Thus, if the input level is
maintained near mid-rail, IOS is very low (<|1nA|), even at 250 C junction temperature.
(2) Output drive current capability is related to output swing magnitude. The HTOP01 will sink and source 20mA minimum over
temperature with the output swinging to within 300mV of either rail. At lesser loads, the output can swing closer to the supply rails;
at loads of 1mA, the output will reach to within 10mV of either rail. For applications where the output remains 500mV away from
the rails, up to 40mA output current is available. Current limiting activates when output current exceeds approximately 50mA.
(3) Supply current consumed by each op amp is PTAT (Proportional To Absolute Temperature) in nature, and as the name
suggests increases proportional to temperature. The 5.0mA maximum current given in the table reflects the maximum current
consumed at 250 C junction temperature by both amplifiers. At 25 C junction temperature, supply current is typically 2mA. PTAT
biasing maintains a near-constant amplifier bandwidth over temperature, a desirable characteristic.
(4) The HTOP01 is designed to handle 50mA output current per amplifier continuously over temperature, with no reduction in
rated product life. In the event of an overload condition, current limiting activates and limits output current to 50mA nominally.
However, due to fabrication process variations, the current limiting threshold can vary up to 30%. Consequently, it is possible to
have a current limiting threshold as high as 65mA. In this situation, if the overload (65mA) is allowed to continue indefinitely at
225 C ambient, there can be a reduction in rated product life. For maximum product life, it is recommended that any overload
output current situation (>50mA) be attended to promptly.
(5) The pseudo-random amplifier auto-zero clock is derived from an on-chip oscillator running at a nominal frequency of 4.0MHz.
(6) With SEL=0 the HTOP01 uses an internally generated clock for offset compensation. Setting SEL=1 and using an external
clock provides superior offset performance over the internal clock. The recommended frequency range for an external clock is
from 4KHz to 100KHz. Optimum performance is achieved with an external clock frequency of approximately 30KHz.
TYPICAL PERFORMANCE PLOTS
Noise Voltage Density vs. Frequency
External Clock = 3kHz
0
100
200
300
400
500
600
700
800
1 Hz 10 Hz 100 Hz 1000 Hz 10000 Hz
Noise Density (nV/root-Hz)
-55C Average
23C Average
225C Average
No clock 23C
