LTC4242
19
4242f
APPLICATIO S I FOR ATIO
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In system board applications, large bypass capacitors
(≥10µF) are recommended at each of the system input
supplies to minimize supply glitches as a result of large
inrush or fault currents.
It is important to put C1, the bypass capacitor for the V
CC
pin as close as possible between the V
CC
and GND pins.
Design Example
Consider a PCI Express Hot Swap application example
with the following power supply requirements:
Table 1. PCI Express Power Supply Requirements
SUPPLY VOLTAGE
MAXIMUM SUPPLY
CURRENT
MAXIMUM LOAD
CAPACITANCE
12V 5.5A 2000µF
3.3V 3.0A 1000µF
3.3V
AUX
375mA 150µF
1. Select an R
SENSE
value for each supply. Calculate the
R
SENSE
value based on the maximum load current and the
lower circuit breaker threshold limit, ΔV
SENSE(CB)(MIN)
. In
a PCI Express connector, fi ve pins are allocated for the
12V supply, three pins for the 3.3V supply and one pin for
3.3V
AUX
. The current rating of a connector pin is 1.1A. If
a 1% tolerance is assumed for the sense resistors, then
the following values of resistances should suffi ce:
Table 2. Sense Resistance Values
VOLTAGE SUPPLY R
SENSE
(1%) I
TRIP(MIN)
I
TRIP(MAX)
12V 8mΩ 5.6A 6.9A
3.3V 13mΩ 3.4A 4.3A
2. Assume no load current at start-up and the inrush current
charges the load capacitance. Compute gate capacitance
with:
C
It
V
GATE
GATE UP
OUT
=
()
•
1
(2)
t
1
is the time to charge up the load capacitor.
With I
GATE(UP)(MAX)
= 13µA and t
1
= 10ms:
a. For 12V Supply, C
GATE
= 11nF
b. For 3.3V Supply, C
GATE
= 39nF
So a value of 15nF and 47nF (±10%) should suffi ce for
the 12V and 3.3V supplies respectively. The worst-case
t
1
and inrush currents are tabulated in Table 3.
Table 3. Worst-Case t
1
and Inrush Current
VOLTAGE SUPPLY t
1(MIN)
t
1(MAX)
MAX I
INRUSH
12V 13ms 40ms 2.4A
3.3V 11ms 34ms 0.4A
For the internal switch, the slew rate (SR) at the 3.3V
AUX
supply output is limited to 1.7V/ms max. The inrush cur-
rent can then be calculated according to:
I
INRUSH(MAX)
= C
LOAD
• SR
MAX
(3)
The inrush current must be lower than 385mA (I
CBAUX(MIN)
)
for proper start-up. Assuming a tolerance of 30% for the
load capacitance, the value of C
LOAD
should not exceed
170µF.
3. Next is the selection of MOSFETs for the 12V and 3.3V
main input supplies. The Si7336ADP’s on resistance is less
than 4mΩ at V
GS
= 4.5V, 25°C and it is a good choice for
3.3V and 12V main supplies.
Since the maximum load for the 3.3V supply is 3A, the
MOSFET may dissipate up to 36mW. The Si7336ADP
has a maximum junction-to-ambient thermal resistance
of 50°C/W. This gives a junction temperature of 51.8°C
when operating at a case temperature of 50°C. Accord-
ing to the Si7336ADP’s Normalized On-Resistance vs
Junction Temperature curve, the device’s on resistance
can be expected to increase by about 12% over its room
temperature value. Recalculation for steady-state R
ON
and junction temperature yield approximately 4.5mΩ
and 52°C, respectively. The voltage drop across the 3.3V
sense resistor and series MOSFET at 3A and at 50°C PCB
temperature is less than 53mV.
The MOSFET dissipates power during inrush charging of
the output load capacitor. Assuming no load current, the
MOSFET’s dissipated power equals the fi nal load capaci-
tor stored energy. Therefore, average MOSFET dissipated
power is:
P
CV
t
ON
LOUT
=
•
•
2
1
2
(4)
