LTC4242
4
4242f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
ON(TH)
ONn, AUXONn Pin Threshold Voltage Rising Edge
●
1.173 1.235 1.297 V
ΔV
ON(TH)
ONn, AUXONn Pin Hysteresis
●
30 70 120 mV
V
ON(RTH)
ONn, AUXONn Pin Reset Threshold Voltage Falling Edge
●
0.5 0.6 0.7 V
I
ON(IN)
ONn, AUXONn Pin Input Current V
ONn
= V
AUXONn
= 1.2V
●
±1 µA
V
EN(TH)
ENn Pin Threshold Voltage ENn Rising
●
1.173 1.235 1.297 V
ΔV
EN(HYST)
ENn Pin Hysteresis
●
30 70 120 mV
I
EN(UP)
ENn Pull-Up Current V
ENn
= 1V
●
–5 –9 –13 µA
V
FON
FONn Pin Logic Threshold
●
0.7 2.6 V
I
SENSE
SENSE Pin Input Current
12V
SENSEn
3V
SENSEn
V
12VSENSEn
= 12V
V
3VSENSEn
= 3.3V
●
●
40
40
100
100
µA
µA
I
OUT
OUT Pin Input Current
12V
OUTn
3V
OUTn
Gate Drive On
V
12VOUTn
= 12V
V
3VOUTn
= 3.3V
●
●
45
27
90
60
µA
µA
R
OUT(DIS)
OUT Pin Discharge Resistance
12V
OUTn
3V
OUTn
AUXOUTn
Gate Drive Off
V
12VOUTn
= 6V
V
3VOUTn
= 2V
V
AUXOUTn
= 2V
●
●
●
350
165
375
700
330
750
1400
660
1500
Ω
Ω
Ω
Output Pins
V
OL
Output Low Voltage
FAULTn, AUXFAULTn, PGOODn,
AUXPGOODn (Note 5)
I
PIN
= 3mA
●
0.14 0.4 V
I
PU
Pull-Up Current
FAULTn, AUXFAULTn, PGOODn,
AUXPGOODn (Note 5)
V
PIN
= 1.5V
●
–5 –9 –13 µA
Slew Rate
SR
AUXOUT
AUXOUTn Slew Rate
●
1.25 1.7 V/ms
Delays
t
PLH(GATE)
Input High (ONn) to GATEs High Prop Delay
●
714 µs
t
PLH(UVL)
Input Supply Low (12V
INn
, 3V
INn
) to GATEs
Low Prop Delay
●
18 36 µs
t
PLH(PG)
Out Low (12V
OUTn
, 3V
OUTn
) to PGOOD High
Prop Delay
●
20 40 µs
t
PHL(SENSE)
Sense Voltage High to GATE Low ΔV
SENSE
= 200mV, C
GATE
= 10nF
●
0.4 1 µs
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
CC
= V
AUXINn
= V
3VINn
= 3.3V, V
12VINn
= 12V, unless otherwise noted.
(Note 2)
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All current into device pins is positive, all current out of the device
pins is negative. All voltages are referenced to GND unless otherwise
specifi ed.
Note 3: An internal clamp limits the GATE pins to a minimum of 5V above
V
OUT
. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: For the QFN package, the AUX FET on resistance is guaranteed by
correlation to wafer level measurements.
Note 5: Available on QFN package only.
