LTC6802-2
13
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operaTion
Figure 4. External Discharge FET Connection (One Cell Shown)
POWER DISSIPATION AND THERMAL SHUTDOWN
The MOSFETs connected to the Pins S1 through S12 can be
used to discharge battery cells. An external resistor should
be used to limit the power dissipated by the MOSFETs. The
maximum power dissipation in the MOSFETs is limited by
the amount of heat that can be tolerated by the LTC6802-2.
Excessive heat results in elevated die temperatures. The
electrical characteristics are guaranteed for die tempera-
tures up to 85°C. Little or no degradation will be observed
in the measurement accuracy for die temperatures up
to 105°C. Damage may occur near 150°C, therefore the
recommended maximum die temperature is 125°C.
To protect the LTC6802-2 from damage due to overheating,
a thermal shutdown circuit is included. Overheating of the
device can occur when dissipating significant power in the
cell discharge switches. The problem is exacerbated when
operating with a large voltage between V
+
and V
or when
the thermal conductivity of the system is poor.
If the temperature detected on the device goes above ap-
proximately 145°C, the configuration registers will be reset
to default states, turning off all discharge switches and
disabling A/D conversions. When a thermal shutdown has
occurred, the THSD bit in the temperature register group
will go high. The bit is cleared by performing a read of the
temperature registers (RDTMP command).
Since thermal shutdown interrupts normal operation, the
internal temperature monitor should be used to determine
when the device temperature is approaching unacceptable
levels.
Cn
MM3Z12VT1
3.3k
Sn
Cn – 1
SI2351DS
15Ω
1W
VISHAY CRCW2512 SERIES
68022 F04
+
DISCHARGING DURING CELL MEASUREMENTS
The primary cell voltage A/D measurement commands
(STCVAD and STOWAD) automatically turn off a cell’s
discharge switch while its voltage is being measured. The
discharge switches for the cell above and the cell below will
also be turned off during the measurement. For example,
discharge switches S4, S5, and S6 will be disabled while
cell 5 is being measured.
In some systems it may be desirable to allow discharging
to continue during cell voltage measurements. The cell
voltage A/D conversion commands STCVDC and STOWDC
allow any enabled discharge switches to remain on during
cell voltage measurements. This feature allows the system
to perform a self test to verify the discharge functionality
and multiplexer operation.
All discharge switches are automatically disabled during
OV and UV comparison measurements.
A/D C
ONVER
TER DIGITAL SELF TEST
Two self-test commands can be used to verify the func-
tionality of the digital portions of the ADC. The self tests
also verify the cell voltage registers and cell temperature
registers. During these self tests a test signal is applied
to the ADC. If the circuitry is working properly the cell
voltage or cell temperature registers will contain identi-
cal codes. For self test 1 the registers will contain 0x555.
For
self
test 2, the registers will contain 0xAAA. The time
required for the self-test function is the same as required
to measure all cell voltages or all temperature sensors.
Perform the self-test function with CDC[2:0] set to 1 in
the configuration register.
U
SING
THE S PINS AS DIGITAL OUTPUTS OR
GA
TE DRIVERS
The S outputs include an internal 10k pull-up resistor.
Therefore the S pins will behave as a digital output when
loaded with a high impedance, e.g., the gate of an external
MOSFET. For applications requiring high battery discharge
currents, connect a discrete PMOS switch device and suit-
able discharge resistor to the cell, and the gate terminal
to the S output pin, as illustrated in Figure 4.
LTC6802-2
14
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+
+
+
+
+
+
+
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
V
LTC6802-2
68022 F05
NEXT HIGHER GROUP OF 7 CELLS
NEXT LOWER GROUP OF 7 CELLS
USING THE LTC6802-2 WITH LESS THAN 12 CELLS
The LTC6802-2 can typically be used with as few as 4 cells.
The minimum number of cells is governed by the supply
voltage requirements of the LTC6802-2. The sum of the
cell voltages must be 10V to guarantee that all electrical
specifications are met.
Figure 5 shows an example of the LTC6802-2 when used to
monitor 7 cells. The lowest C inputs connect to the 7 cells
and the upper C inputs connect to V
+
. Other configura-
tions, e.g., 9 cells, would be configured in the same way:
the lowest C inputs connected to the battery cells and the
unused C inputs connected to V
+
. The unused inputs will
result in a reading of 0V for those channels.
The ADC can also be commanded to measure a stack of
cells by making 10 or 12 measurements, depending on the
state of the CELL10 bit in the control register. Data from all
10 or 12 measurements must be downloaded when read-
ing the conversion results. The ADC can be commanded
to measure any individual cell voltage.
Figure 5. Monitoring 7 Cells with the LTC6802-2
applicaTions inForMaTion
USING THE GENERAL PURPOSE INPUTS/OUTPUTS
(GPIO1, GPIO2)
The LTC6802-2 has two general purpose digital inputs/out-
puts. By writing a GPIO configuration register bit to a logic
low, the open-drain output can be activated. The GPIOs
give the user the ability to turn on/off circuitry around the
LTC6802-2. One example might be a circuit to verify the
operation of the system.
When a GPIO configuration bit is written to a logic high,
the corresponding GPIO pin may be used as an input.
The read back value of that bit will be the logic level that
appears at the GPIO pin.
When the MMB pin is low, the GPIO pins and the WDTB
pin are treated as inputs that set the number of cells to
be monitored. See the Monitor Mode section.
WA
TCHDOG
TIMER CIRCUIT
The LTC6802-2 includes a watchdog timer circuit. If no
activity is detected on the SCKI pin for 2.5 seconds, the
WDTB open-drain output is asserted low. The WDTB pin
remains low until an edge is detected on the SCKI pin.
When the watchdog timer circuit times out, the configura-
tion bits are reset to their default (power-up) state.
In the power-up state, the S outputs are off. Therefore, the
watchdog timer provides a means to turn off cell discharg-
ing should communications to the MPU be interrupted.
The IC is in the minimum power standby mode after a
time out. Note that externally pulling the WDTB pin low
will not reset the configuration bits.
The watchdog timer operation is disabled when MMB
is low.
When reading the configuration register, byte CFG0 bit 7
will reflect the state of the WDTB pin.
R
EVISION
CODE
The temperature register group contains a 3-bit revision
code. If software detection of device revision is neces-
sary, then contact the factory for details. Otherwise, the
code can be ignored. In all cases, however, the values of
all bits must be used when calculating the packet error
code (PEC) CRC byte on data reads.
LTC6802-2
15
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applicaTions inForMaTion
MODES OF OPERATION
The LTC6802-2 has three modes of operation: standby,
measure and monitor. Standby mode is a power saving state
where all circuits except the serial interface are turned off.
In measure mode, the LTC6802-2 is used to measure cell
voltages and store the results in memory. Measure mode
will also monitor each cell voltage for overvoltage (OV)
and undervoltage (UV) conditions. In monitor mode, the
device will only monitor cells for UV and OV conditions.
A signal is output on the SDO pin to indicate the UV/OV
status. The serial interface is disabled.
Standby Mode
The LTC6802-2 defaults (powers up) to standby mode.
Standby mode is the lowest possible supply current state.
All circuits are turned off except the serial interface and
the voltage regulator. The LTC6802-2 can be programmed
for standby mode by setting configuration bits CDC[2:0]
to 0. If the part is put into standby mode while ADC
measurements are in progress, the measurements will
be interrupted and the cell voltage registers will be in an
indeterminate state. To exit standby mode, the CDC bits
must be written to a value other than 0.
Measure Mode
The LTC6802-2 is in measure mode when the CDC bits are
programmed with a value from 1 to 7. The IC monitors
each cell voltage and produces an interrupt signal on the
SDO pin indicating all cell voltages are within the UV and
OV limits. There are two methods for indicating the UV/OV
interrupt status: toggle polling (using a 1kHz output signal)
and level polling (using a high or low output signal). The
polling methods are described in the Serial Port section.
The UV/OV limits are set by the VUV and VOV values in
the configuration registers. When a cell voltage exceeds
the UV/OV limits a bit is set in the flag register. The UV
and OV flag status for each cell can be determined using
the Read Flag Register Group.
If fewer than 12 cells are connected to the LTC6802-2
then it is necessary to mask the unused input channels.
The MCxI bits in the configuration registers are used to
mask channels. If the CELL10 bit is high, then the inputs
for cells 11 and 12 are automatically masked.
The LTC6802-2 can monitor UV and OV conditions con-
tinuously. Alternatively, the duty cycle of the UV and OV
comparisons can be reduced or turned off to lower the
overall power consumption. The CDC bits are used to
control the duty cycle.
To initiate cell voltage measurements while in measure
mode, a Start A/D Conversion and Poll Status command
must be sent. After the command has been sent, the
LTC6802-2 will send the A/D converter status using either
the toggle polling or the level polling method, as described
in the Serial Port section. If the CELL10 bit is high, then
only the bottom 10 cell voltages will be measured, thereby
reducing power consumption and measurement time. By
default the CELL10 bit is low, enabling measurement of all
12 cell voltages. During cell voltage measurement com-
mands, UV and OV flag conditions, reflected in the flag
register group, are also updated. When the measurements
are complete, the part will go back to monitoring UV and
OV conditions at the rate designated by the CDC bits.
Monitor Mode
The LTC6802-2 can be used as a simple monitoring circuit
with no serial interface by pulling the MMB pin low. When
in this mode, the interrupt status is indicated on the SDO
pin using the toggle polling mode described in the Serial
Port section. Unlike serial port polling commands, however,
the toggling is independent of the state of the CSBI pin.
When the MMB pin is low, all the device configuration
values are reset to the default states shown in Table 15
Memory Bit Descriptions. When MMB is held low the
VUV, VOV, and CDC register values are ignored. Instead
VUV and VOV use factory-programmed setings. CDC is
set
to
state 5. The number of cells to be monitored is set
by the logic levels on the WDTB and GPIO pins, as shown
in Table 1.

LTC6802IG-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Individually Addressable SPI
Lifecycle:
New from this manufacturer.
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