AD8015
REV. A
–3–
.
V1
+V
S
CLOCK
RECOVERY
LPF:
3dB@
0.7 x F
LPF:
3dB@
0.7 x F
QUANTIZER
R > 40Ω
C1 >100pF
4.5V < V
S
< 11V
CLK
DATA
RR
C1
10kΩ
5
6
7
8
4
3
2
1
AD8015
50Ω
+1
G = 3
G = 30
50Ω
+1
– + +V
S
1.7V
1.7V
+V
S
Figure 3. Fiber Optic Receiver Application: Photodiode
Referred to Positive Supply
PHOTODIODE REFERRED TO NEGATIVE SUPPLY
Figure 4 shows the AD8015 used in a circuit where the photo-
diode is referred to the negative supply. This results in a larger
back bias voltage than when referring the photodiode to the
positive supply. The larger back bias voltage on the photodiode
decreases the photodiode’s capacitance thereby increasing its
bandwidth. The R2, C2 network shown in Figure 4 is added to
decouple the photodiode to the positive supply. This improves
PSRR.
+V
S
1.7V
+V
S
R2
C2
R > 40Ω
C1 >100pF
4.5V < V
S
< 11V
R2 AND C2 OPTIONAL
FOR IMPROVED PSRR
V1
+V
S
CLOCK
RECOVERY
LPF:
3dB@
0.7 x F
LPF:
3dB@
0.7 x F
QUANTIZER
CLK
DATA
RR
C1
10kΩ
5
6
7
8
4
3
2
1
AD8015
50Ω
+1
G = 3
G = 30
50Ω
+1
– + +V
S
1.7V
Figure 4. Fiber Optic Receiver Application: Photodiode
Referred to Negative Supply
FIBER OPTIC SYSTEM NOISE PERFORMANCE
The AD8015 maintains 26.5 nA referred to input (RTI) to 100
MHz. Calculations below translate this specification into mini-
mum power level and bit error rate specifications for SONET
and FDDI systems. The dominant sources of noise are: 10 kΩ
feedback resistor current noise, input bipolar transistor base
current noise, and input voltage noise.
The AD8015 has dielectrically isolated devices and bond pads
that minimize stray capacitance at the I
IN
pin. Input voltage
noise is negligible at lower frequencies, but can become the
dominant noise source at high frequencies due to I
IN
pin stray
capacitance. Minimizing the stray capacitance at the I
IN
pin is
critical to maintaining low noise levels at high frequencies. The
pins surrounding the I
IN
pin (Pins 1 and 3) have no internal
connection and should be left unconnected in an application.
This minimizes I
IN
pin package capacitance. It is best to have no
ground plane or metal runs near Pins 1, 2, and 3 and to mini-
mize capacitance at the I
IN
pin.
The AD8015AR (8-pin SOIC) I
IN
pin total stray capacitance is
0.4 pF without the photodiode. Photodiodes used for SONET
or FDDI systems typically add 0.3 pF, resulting in roughly
0.7 pF total stray capacitance.
PIN CONFIGURATION
10kΩ
5
6
7
8
4
3
2
1
AD8015
50Ω
+1
NC
I
IN
NC
V
BYP
–V
S
–OUTPUT
+OUTPUT
+V
S
G = 3
G = 30
NC = NO CONNECT
50Ω
+1
– + +V
S
1.7V
METALIZATION PHOTOGRAPH
Dimensions shown in microns. Not to scale.
FIBER OPTIC RECEIVER APPLICATIONS
In a fiber optic receiver, the photodiode can be placed from the
I
IN
pin to either the positive or negative supply. The AD8015
converts the current from the photodiode to a differential volt-
age in these applications. The voltage at the V
BYP
pin is ≈1.8 V
below the positive supply. This node must be bypassed with a
capacitor (C1 in Figures 3 and 4 below) to the signal ground. If
large levels of power supply noise exist, then connecting C1 to
+V
S
is recommended for improved noise immunity. For opti-
mum performance, choose C1 such that C1 > 1/(2 π × 1000 ×
f
MIN
); where f
MIN
is the minimum useful
frequency in Hz.
PHOTODIODE REFERRED TO POSITIVE SUPPLY
Figure 3 shows the AD8015 used in a circuit where the photo-
diode is referred to the positive supply. The back bias voltage on
the photodiode is ≈1.8 V. This method of referring the photo-
diode provides greater power supply noise immunity (PSRR)
than referring the photodiode to the negative supply. The signal
path is referred to the positive rail, and the photodiode capaci-
tance is not modulated by high frequency noise that may exist
on the negative rail.
OPTIONAL
+V
S
CONNECTION
+OUTPUT
–OUTPUT
I
IN
V
BYP
973µ
998µ
+V
S
838µ
–V
S
813µ
NOTE:
FOR BEST PERFORMANCE ATTACH PACKAGE
SUBSTRATE TO +V
S
.
MATERIAL AT BACK OF DIE IS SILICON. USE OF
+V
S
OR –V
S
FOR DIE ATTACH IS ACCEPTABLE.
