MT36HTF25672FZ-667G1N8 Datasheet MT36HTF1G72FZ-80EC1D6, MT36HTF25672FZ-667G1N8, MT36HTF51272FZ-667H1N8 | P7-P9

General Description

Micron’s FBDIMM devices adhere to the currently proposed industry specifications for

FBDIMMs. The following specifications contain detailed information on FBDIMM de-

sign, interfaces, and theory of operation and are listed here for the system designers’

convenience. Refer to the JEDEC Web site for available specifications.

•

FBDIMM Design Specification – pending JEDEC approval

•

FBDIMM: Architecture and Protocol – JESD206

•

FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20

•

Design for Test, Design for Validation (DFx) Specification

•

Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C,

page 4.1.2.7-1

This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that

has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from

the channel behind an AMB on the FBDIMM. Memory device capacity remains high,

and total memory capacity scales with DDR2 SDRAM bit density.

As shown in the System Block Diagram, the FBDIMM channel provides a communica-

tion path from a host controller to an array of DDR2 SDRAM devices, with the DDR2

SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2

SDRAM devices from the channel enhances the communication path and significantly

increases the reliability and availability of the memory subsystem.

Advanced Memory Buffer

The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB

component, located in the center of each FBDIMM, acts as a repeater and buffer for all

signals and commands exchanged between the host controller and DDR2 SDRAM devi-

ces, including data input and output. The AMB communicates with the host controller

and adjacent FBDIMMs on a system board using an industry-standard, high-speed, dif-

ferential, 1.5V, point-to-point interface. The AMB also enables buffering of memory

traffic to support large memory capacities. Refer to the JEDEC JESD82-20 specification

for further information.

2GB, 4GB, 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

General Description

PDF: 09005aef83d491e1

htf36c256_512_1gx72fz.pdf - Rev. B 10/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in the device data sheet is not implied. Exposure to

absolute maximum rating conditions for extended periods may adversely affect reliability.

Table 8: Absolute Maximum Ratings

Parameter Symbol Min Max Units Notes

Voltage on any pin relative to V

, V

OUT

–0.3 +1.75 V 1

Voltage on V

pin relative to V

–0.3 +1.75 V

Voltage on V

pin relative to V

–0.5 +2.3 V

Voltage on V

pin relative to V

–0.5 +2.3 V

DDR2 SDRAM device operating case temperature T

0 +95 °C 2, 3

AMB device operating temperature 0 +110 °C

Notes:

1. V

should not be greater than V

2. T

is specified at 95°C only when using 2X refresh timing (

REFI = 7.8µs at or below 85°C;

REFI = 3.9µs above 85°C); refer to the DDR2 SDRAM component data sheet.

3. See applicable DDR2 SDRAM component data sheet for

REFI and extended mode regis-

ter settings. The

REFI parameter is used to specify the doubled refresh interval necessa-

ry to sustain <85°C operation.

Table 9: Input DC Voltage and Operating Conditions

Parameter Symbol Min Nom Max Units Notes

AMB supply voltage V

1.46 1.5 1.54 V

DDR2 SDRAM supply voltage V

1.7 1.8 1.9 V

Termination voltage V

0.48 × V

0.5 × V

0.52 × V

EEPROM supply voltage V

DDSPD

3 3.3 3.6 V 1

SPD input high (logic 1) voltage V

IH(DC)

2.1

–

DDSPD

V 2

SPD input low (logic 0) voltage V

IL(DC)

– –

0.8 V 2

RESET input high (logic 1) voltage V

IH(DC)

– –

V 3

RESET input low (logic 0) voltage V

IL(DC)

– –

0.5 V 2

Leakage current (RESET) l

–90

–

+90 µA 3

Leakage current (link) l

–5

–

+5 µA 4

Notes:

1. Applies to AMB and SPD.

2. Applies to serial memory buffer (SMB) and SPD bus signals.

3. Applies to AMB CMOS signal RESET#.

4. For all other AMB-related DC parameters, please refer to the high-speed differential link

interface specification.

2GB, 4GB, 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Electrical Specifications

PDF: 09005aef83d491e1

htf36c256_512_1gx72fz.pdf - Rev. B 10/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 10: Clock Rates

FBDIMM Link Data Rate Reference Clock DRAM Clock DRAM Data Rate

3.2 Gb/s 133 MHz 266 MHz 533 Mb/s

4.0 Gb/s 167 MHz 333 MHz 666 Mb/s

4.8 Gb/s 200 MHz 400 MHz 800 Mb/s

Note:

1. DDR2 components may exceed the listed module speed grades; module may not be avail-

able in all listed speed grades

2GB, 4GB, 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Electrical Specifications

PDF: 09005aef83d491e1

htf36c256_512_1gx72fz.pdf - Rev. B 10/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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MT36HTF25672FZ-667G1N8

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Description:

MODULE DDR2 SDRAM 2GB 240FBDIMM

Lifecycle:

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MT36HTF25672FZ-667G1N8

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