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MT36HTF51272FZ-667H1N8

P1-P3P4-P6P7-P9P10-P12P13-P14
IDD Specifications and Conditions
Table 11: I
DD
Conditions
Symbol Condition
I
DD_IDLE_0
Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel ena-
bled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2
SDRAM clock active
I
DD_IDLE_1
Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels
enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
I
DD_ACTIVE_1
Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secon-
dary channels enabled; DDR2 SDRAM clock active; CKE HIGH
I
DD_ACTIVE_2
Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream
DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM
clock active; CKE HIGH; Command and address lines stable
I
DD_TRAINING
Training: Primary and secondary channels enabled; 100% toggle on all channel lanes;
DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM
clock active
I
DD_IBIST
IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secon-
dary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
I
DD_EI
Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel
disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and
CKE driven LOW
Note:
1. Actual test conditions may vary from published JEDEC test conditions.
Table 12: I
DD
Specifications – All Densities DDR2-800
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
TBD TBD TBD TBD TBD TBD TBD mA
I
DD
TBD TBD TBD TBD TBD TBD TBD mA
Total power TBD TBD TBD TBD TBD TBD TBD W
Table 13: I
DD
Specifications – 2GB DDR2-667
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2600 3400 3900 3700 4000 4500 2500 mA
I
DD
2520 2520 4655 2520 2520 2520 452 mA
Total power 8.8 10.1 15 10.6 11.1 11.9 4.8 W
Table 14: I
DD
Specifications – 4GB DDR2-667
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2600 3400 3900 3700 4000 4500 2500 mA
I
DD
2340 2340 3995 2340 2340 2340 452 mA
Total power 8.5 9.8 13.7 10.3 10.7 11.5 4.8 W
2GB, 4GB, 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
IDD Specifications and Conditions
PDF: 09005aef83d491e1
htf36c256_512_1gx72fz.pdf - Rev. B 10/10 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Table 15: I
DD
Specifications – 8GB DDR2-667
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2600 3400 3900 3700 4000 4500 2500 mA
I
DD
2800 2800 4475 2800 2800 2800 632 mA
Total power 9.5 10.8 14.6 11.3 11.8 12.5 5.1 W
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 16: Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition Symbol Min Max Units
EEPROM and AMB supply voltage V
DDSPD
3 3.6 V
Input high voltage: Logic 1; all inputs V
IH
V
DDSPD
× 0.7 V
DDSPD
+ 0.5 V
Input low voltage: Logic 0; all inputs V
IL
–0.6 V
DDSPD
× 0.3 V
Output low voltage: I
OUT
= 3mA V
OL
–
0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.10 3 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 3 µA
Standby current I
SB
1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz I
CCR
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz I
CCW
2 3 mA
Table 17: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3
–
µs
Data-out hold time
t
DH 200
–
ns
SDA and SCL fall time
t
F
–
300 ns 2
Data-in hold time
t
HD:DAT 0
–
µs
Start condition hold time
t
HD:STA 0.6
–
µs
Clock HIGH period
t
HIGH 0.6
–
µs
Noise suppression time constant at SCL, SDA inputs
t
I
–
50 ns
Clock LOW period
t
LOW 1.3
–
µs
SDA and SCL rise time
t
R
–
0.3 µs 2
SCL clock frequency
f
SCL
–
400 kHz
Data-in setup time
t
SU:DAT 100
–
ns
Start condition setup time
t
SU:STA 0.6
–
µs 3
Stop condition setup time
t
SU:STO 0.6
–
µs
2GB, 4GB, 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
Serial Presence-Detect
PDF: 09005aef83d491e1
htf36c256_512_1gx72fz.pdf - Rev. B 10/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Table 17: Serial Presence-Detect EEPROM AC Operating Conditions (Continued)
Parameter/Condition Symbol Min Max Units Notes
WRITE cycle time
t
WRC
–
10 ms 4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
2GB, 4GB, 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM
Serial Presence-Detect
PDF: 09005aef83d491e1
htf36c256_512_1gx72fz.pdf - Rev. B 10/10 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P14

MT36HTF51272FZ-667H1N8

Mfr. #:
Buy MT36HTF51272FZ-667H1N8
Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 4GB 240FBDIMM
Lifecycle:
New from this manufacturer.
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