MAX394
Low-Voltage, Quad, SPDT,
CMOS Analog Switch
6 _______________________________________________________________________________________
PARAMETER SYMBOL
MIN TYP MAX
(Note 2)
UNITSCONDITIONS
Input Current with Input
Voltage Low
I
INL
µA
Negative Supply Current I-
-1.0 -0.01 +1.0
µA
Positive Supply Current I+ -1.0 +0.01 +1.0 µA
All channels on or off, V
IN
= 0V or V+,
V+ = 3.6V, V- = 0V
All channels on or off, V
IN
= 0V or V+,
V+ = 3.6V, V- = 0V
V
IN
= 0.8V, all others = 2.4V -1.0 +0.005 +1.0
ELECTRICAL CHARACTERISTICS—Single +3.3V Supply (continued)
(V+ = 3.0V to 3.6V, GND = 0V, V
INH
= 2.4V, V
INL
= 0.8V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Power-Supply Range V+ 2.7 16 V
Input Current with Input
Voltage High
I
INH
µAV
IN
= 2.4V, all others = 0.8V -1.0 +0.005 +1.0
Turn-On Time (Note 3) t
ON
400 nsV
COM
= 1.5V, Figure 2
Turn-Off Time (Note 3) t
OFF
150 nsV
COM
= 1.5V, Figure 2
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
Break-Before-Make Delay
(Note 3)
Charge Injection (Note 3) V
CTE
15pC
C
L
= 1.0nF, V
GEN
= 0V,
R
GEN
= 0Ω, Figure 6
t
D
520 nsFigure 5
DIGITAL LOGIC INPUT
DYNAMIC
SUPPLY
Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in
this data sheet.
Note 3: Guaranteed by design.
Note 4: ΔR
ON
= ΔR
ON
(max) - ΔR
ON
(min). On-resistance match between channels and flatness are guaranteed only with
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
Note 5: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temperature.
Note 6: See Figure 6. Off-isolation = 20log
10
V
COM
/V
NC
or V
NO
, V
COM
= output, V
NC
or
NO
= input to off switch.
Note 7: Between any two switches. See Figure 3.
Note 8: Leakage testing at single supply is guaranteed by testing with dual supplies.
