QT411-ISSG Datasheet QT411-ISSG | P4-P6

element. The position data ceases to be reported when touch

detection is no longer sensed.

1.6 Calibration

Calibration is possible via two methods:

1) Power up or power cycling (there is no reset input).

2) On command from the host via the SPI port

(Command 0x01: see Section 3.3.2).

The calibration period requires 10 burst cycles, which are

executed automatically without the need for additional SPI

commands from the host. The spacing between each Cal

burst is 1ms, and the bursts average about 31ms each, i.e.

the Cal command requires ~325ms to execute. The power up

calibration has 6 extra bursts to allow for power supply

stabilization, and requires a total of ~550ms to begin normal

operation.

Calibration should be performed when there is no hand

proximity to the element, or the results may be in error.

Should this happen, the error flag (bit 1 of the standard

response, see Section 3.3) will activate when the hand is

withdrawn. In most cases this condition will self-correct if drift

compensation is used, and it can thus be ignored. See

Section 1.9 below.

Note: During calibration, the device cannot communicate.

DRDY will remain low during this interval.

1.7 Sensitivity Setting

The sensitivity of the slider area to finger detection is

dependent on the values of the three Cs capacitors (Section

2.2) and the threshold setting (Section 3.3.5). Larger values

of Cs increase sensitivity and also reduce granularity (missing

codes), at the expense of higher power consumption due to

longer acquisition bursts.

The threshold setting can be used to fine tune the sensitivity

of the sensing element. When setting the threshold, use the

smallest finger size for which detection is desired (normally a

6mm diameter spot), and probe at one of the two center

connection points where sensitivity is weakest. The linear

stretches between connection points are generally slightly

higher in sensitivity due to the collection of charge from two

channels.

A ‘standard finger’ probe can be made by taking a piece of

metal foil of the required diameter, gluing it on the end of a

cylinder of sponge rubber, and connecting it to ground with a

wire. This probe is pressed against the panel centered on one

of the middle two connection points; the threshold parameter

is iterated until the sensor just detects. It is important to push

the probe into the panel quickly and not let it linger near the

electrode afterwards, so that the drift compensation

mechanism does not artificially create a threshold offset

during the iteration process. Between threshold changes, the

probe must be removed to at least 100mm from the panel.

1.8 Drift Compensation

The device features an ability to compensate for slow drift

due to environmental factors such as temperature changes or

humidity. Drift compensation is performed under host control

via a special drift command. See Section 3.3.3 for further

details.

1.9 Error Status

An error flag status is provided via a special command. An

error can only occur when a finger was touching the sensing

strip during power-on or recalibration, and then removed. In

this sequence of events, the finger is ‘calibrated away’ and is

not recognized as a touch. When the finger is removed, the

signals from the device are inverted and a position is reported

as though the strip has been touched. However, this position

report is in error.

After any calibration event (i.e. a power-on cycle or a CAL

command) the next detection event should be checked to see

if it is in error by using the special error command. If it an

error is reported, the device should be immediately calibrated

again to restore normal function (Section 3.3.2).

2 Wiring & Parts

The device should be wired according to Figure 1-1. An

examples of a PCB layout is shown in Figure 1-3.

2.1 Electrode Construction

The strip electrode should be a resistive element of between

200K to 500K ohms (400K nominal target value) between

each set of connection points, of a suitable length and width.

Under heavy capacitive loading (for example if the element

4 QT411-ISSG R6.01/1005

Figure 1-3 Conventional PCB Layout (1-sided)

Copper side faces away from the panel; the bare side is glued to the inside of the product.

Table 1-2 Recommended Cs vs. Materials

100nF-

4.0

47nF-

3.0

39nF100nF

2.5

22nF47nF

1.5

10nF22nF

0.8

5.6nF10nF

0.4

Borosilicate glass

(

εε

=4.8)

Acrylic

(

εε

=2.8)

Thickness,

must be placed immediately over a ground plane within a

millimeter), the resistance might need to be lowered. Observe

the sensing pulses for flatness on their tops in the middle of a

segment using a small coin and scope probe to make sure

the pulses fully settle before the falling edge (see app note

AN-KD02 Figure 7).

The electrode can be made of a series chain of discrete

resistors with copper pads on a PCB, or from ITO (Indium Tin

Oxide, a clear conductor used in LCD panels and touch

screens) over a display. Thick-film carbon paste can also be

used, however linearity might be a problem as these films are

notoriously difficult to control without laser trimming or

scribing.

The linearity of the sensing strip is governed largely by the

linearity and consistency of the resistive element. Position

accuracy to within 5% is routinely achievable with good grade

resistors and a uniform construction method.

2.2 Cs Sample Capacitors

Cs1, Cs2 and Cs3 are the charge sensing sample capacitors;

normally they are identical in nominal value. They should be

of type X7R dielectric.

The optimal Cs values depend on the thickness of the panel

and its dielectric constant. Lower coupling to a finger caused

by a low dielectric constant and/or thicker panel will cause the

position result to become granular and more subject to

position errors. The ideal panel is made of thin glass. The

worst panel is thick plastic. Granularity due to poor coupling

can be compensated for by the use of larger values of sample

capacitors.

A table of suggested values for no missing position values is

shown in Table 1-2. Values of Cs smaller than those shown in

the table can cause skipping of position codes. Code skipping

may be acceptable in many applications where fine position

data is not required. Smaller Cs capacitors have the

advantage of requiring shorter acquisition bursts and hence

lower power drain.

Larger values of Cs improve granularity at the expense of

longer burst lengths and hence more average power.

Cs1, Cs2 and Cs3 should be X7R type, matched to within

10% of each other (ie, 5% tolerance) for best accuracy. The

PCB reference layout (Figure 1-3) is highly recommended. If

the Cs capacitors are poorly matched, position accuracy will

be affected and there could also be missing codes.

2.3 Rs Resistors

See Figure 1-1. Rs1, Rs2, and Rs3 are low value (typically

4.7K) resistors used to suppress the effects of ESD and

assist with EMC compliance. They are optional in most

cases.

In addition, there are two 8.2K resistors required to split

channel SNS3B into the two constituent ends. These two

resistors should be placed close to the ends of the slider

strip.

2.4 Power Supply

The usual power supply considerations with QT parts applies

also to the QT411. The power should be very clean and come

from a separate regulator if possible. This is particularly

critical with the QT411 which reports continuous position as

opposed to just an on/off output.

A ceramic 0.1µF bypass capacitor should be placed very

close to the power pins of the IC.

Regulator stability: Most low power LDO regulators have

very poor transient stability, especially when the load

transitions from zero current to full operating current in a few

microseconds. With the QT411 this happens when the device

comes out of sleep mode. The regulator output can suffer

from hundreds of microseconds of instability at this time,

which will have a negative effect on acquisition accuracy.

To assist with this problem, the QT411 waits 500µs after the

400µs taken to come out of sleep mode before acquiring to

allow power to fully stabilize. This delay is not present before

an acquisition burst if there is no preceding sleep state.

Use an oscilloscope to verify that Vdd has stabilized to within

5mV or better of final settled voltage before a burst begins.

The QT411 has specially enhanced power supply rejection

built in. This means that it is often possible to share the

regulator with other circuits. However, it is always advised to

be sure that Vdd is free from spikes and transients, and is

filtered sufficiently to prevent detection problems.

During development it is wise to first design a regulator onto

the PCB just for (and next to) the QT411, but allow for it to be

‘jumpered out’. If in development it is clear that there are no

problems with false detection or ‘angle noise’ even without a

separate regulator for the QT411, then the regulator can be

safely omitted.

2.5 PCB Layout and Mounting

One form of PCB layout is shown in Figure 1-3. This is a

1-sided board; the blank side is simply adhered to the inside

of a 2mm thick (or less) control panel. Thicker panels can be

tolerated with additional position error due to capacitive ‘hand

shadow’ effects and will also have poorer EMC performance.

The Figure 1-3 layout uses a series copper pads connected

with intervening series resistors in a row. The total resistance

between any two connection points can be in the range of

100K to 500K, with ~400K being a suitable target value .

Resistance values at the higher end of this range will

generate more sensitivity provided there is no ground plane

close underneath the electrode strip.

A human finger interpolates between the copper pads (if the

pads are narrow enough) to make a smooth output with no

apparent steps. The lateral dimension along the centre of

each electrode should be no wider than the expected

smallest diameter of finger touch, to prevent stepping of the

position response (if it matters).

It is also possible create an interleaved electrode array with

only 3 resistors between each channel’s connection point on

the strip. Interleaving eliminates stepping while reducing the

number of required resistors. Consult Quantum for further

details.

Resistive inks (such as ITO, Agfa Orgacon

etc.) can also be

used if the resistance between connection points is in the

recommended range.

The electrode strip can be made in various lengths up to at

least 80mm. The electrode width should be about 12mm wide

or more, as a rule. The strip can also be an arc or other

irregular shape. For a 360 degree wheel, use the QT511 or

consult Quantum for other options.

5 QT411-ISSG R6.01/1005

The SMT components should be oriented perpendicular to

the direction of bending so that they do not fracture when the

PCB is flexed during bonding to the panel.

Additional ground area or a ground plane on the PCB will

compromise signal strength and is to be avoided. A single

sided PCB can be made of FR-2 or CEM-1 for low cost.

‘Handshadow’ effects: With thicker and wider panels an

effect known as ‘handshadow’ can become noticeable. If the

capacitive coupling from finger to electrode element is weak,

for example due to a narrow electrode width or a thick, low

dielectric constant panel, the remaining portion of the human

hand can contribute a significant portion of the total

detectable capacitive load. This will induce an offset error,

which will depend on the proximity and orientation of the hand

to the remainder of the element. Thinner panels and those

with a smaller diameter will reduce this effect since the finger

contact surface will strongly domina te the total signal, and the

remaining handshadow capacitance will not contribute

significantly to create an error offset.

PCB Cleanliness: All capacitive sensors should be treated

as highly sensitive circuits which can be influenced by stray

conductive leakage paths. QT devices have a basic

resolution in the femtofarad range; in this region, there is no

such thing as ‘no clean flux’. Flux absorbs moisture and

becomes conductive between solder joints, causing signal

drift and resultant false detections or temporary loss of

sensitivity. Conformal coatings will trap in existing amounts of

moisture which will then become highly temperature

sensitive.

The designer should specify ultrasonic cleaning as part of the

manufacturing process, and in extreme cases, the use of

conformal coatings after cleaning.

2.6 ESD

EMC and Related Issues

Please refer to Quantum app note AN-KD02 for further

information on ESD and EMC matters.

3 Serial Communications

The serial interface is a SPI slave-only mode type which is

compatible with multi-drop operation, i.e. the MISO pin will

float after a shift operation to allow other SPI devices (master

or slave) to talk over the same bus. There should be one

dedicated /SS line for each QT411 from the host controller.

A DRDY (‘data ready’) line is used to indicate to the host

controller when it is possible to talk to the QT411.

3.1 Power-up Timing Delay

Immediately after power-up, DRDY floats for approximately

20ms, then goes low. The device requires ~525ms thereafter

before DRDY goes high again, indicating that the device has

calibrated and is able to communicate.

From power up to first communication, allow a total of 550ms

in startup delay.

3.2 SPI Timing

The SPI interface is a five-wire slave-only type; timings are

found in Figure 3-1. The phase clocking is as follows:

5kHz min, 40kHz maxClock rate:

8 bits, MSB shifts firstBit length & order:

Low from QT inhibits hostData Ready DRDY:

Negative level frame from hostSlave Select /SS:

Rising edge of CLK from hostInput data read on:

Falling edge of CLK from hostData out changes on:

HighClock idle:

The host can shift data to and from the QT on the same cycle

(with overlapping commands). Due to the nature of SPI, the

return data from a command or request is always one SPI

cycle behind.

An acquisition burst always happens about 920µs after /SS

goes high after coming out of Sleep mode . SPI clocking

lasting more than 15ms can cause the chip to self-reset.

6 QT411-ISSG R6.01/1005

Figure 3-1 SPI Timing Diagram

~31ms ~31ms

Acquire Burs

<1ms <1ms

Sleep Mode awake low-power sleep awake sleep

400us typ

3-state if left to float

DRDY from QT >13us, <100us

>12us, <100us

>12us, <100us >20us

<35us >1us, <5us

SS from host

sleep until automatic wake (~3s)

wake up on /SS line

CLK from Host

data hold >=12us

after last clock

Host Data Output

(Slave Input - MOSI)

response byte

QT Data Output 3-state 3-state

(Slave Out - MISO)

output driven output floats

<12us after /SS before DRDY

goes low goes low

0? 7654321

76543210

Data shifts out on falling edge

Data sampled on rising edge

command byte

<10us delay

edge to data

P1-P3 P4-P6 P7-P9 P10-P12

QT411-ISSG

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