2.4GHz DSSS SPI Radio for External Antenna AWS24S
Data Sheet
Artaflex Inc. DSAWS24S Rev 5v0
215 Konrad Crescent Revised Jan 23, 2009
Markham, Ontario, Canada
L3R8T9 Page 4 of 14 http://www.artaflexmodules.com
905-479-0148
4.3 Auto Transaction Sequencer (ATS)
The AWS24S module provides automated support for transmission and reception of acknowledged data packets.
When transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the
packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet and then
automatically reverts to sleep mode or idle mode when either an ACK packet is received, or a timeout period expires.
Similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, and then
automatically transitions to transmit mode, transmits an ACK packet, and then switches back to receive mode to await the next
packet. The contents of the packet buffers are not affected by the transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without any need for micro controller firmware action; to transmit data the
micro controller simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when
receiving packets in transaction mode, firmware simply needs to retrieve the fully received packet in response to an interrupt
request indicating reception of a packet.
4.4 Data Rates
By combining the DATA_CODE_ADR code lengths and data transmission modes described above, the AWS24S supports the
following modes and data rates.
Table 1 - Data Rates
RF Transmission Mode Raw Data Rate kbps
GFSK 1,000.00
32-Chip 8DR 250.00
64-chip 8DR
[2]
125.00
32-chip DDR
[3]
62.50
64-chip DDR
[3]
31.25
64-chip SDR
[2,3]
15.63
5 SPI Communication
The AWS24S has an SPI interface supporting communications between an application MCU and one or more slave devices
(including the AWS24S). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin
interfacing. The SPI communications interface consists of Slave Select (
), Serial Clock (SCK), and Master Out- Slave In
(MOSI), Master In-Slave Out (MISO), or Serial Data (SDAT).
The SPI communications is as follows:
¾ Command Direction (bit 7) = “1” enables SPI write transaction. A “0” enables SPI read transactions.
¾ Command Increment (bit 6) = “1” enables SPI auto address increment. When set, the address field automatically
increments at the end of each data byte in a burst access, otherwise the same address is accessed.
¾ Six bits of address.
¾ Eight bits of data.
The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO pin. The active-low Slave Select (
) pin must be asserted to
initiate an SPI transfer.
The application MCU can initiate SPI data transfers via a multi byte transaction. The first byte is the Command/Address byte,
and the following bytes are the data bytes as shown in Figure 2 through Figure 5.
