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U440-E3

P1-P3P4-P6P7-P7
U440/441
Vishay Siliconix
Document Number: 70251
S-04031—Rev. D, 04-Jun-01
www.vishay.com
8-1
Matched N-Channel JFET Pairs
PRODUCT SUMMARY
Part Number V
GS(off)
(V) V
(BR)GSS
Min (V) g
fs
Min (mS) I
G
Typ (pA) jV
GS1
– V
GS2
j Max (mV)
U440 –1 to –6 –25 4.5 –1 10
U441 –1 to –6 –25 4.5 –1 20
FEATURES BENEFITS APPLICATIONS
D Two-Chip Design
D High Slew Rate
D Low Offset/Drift Voltage
D Low Gate Leakage: 1 pA
D Low Noise
D High CMRR: 85 dB.
D Minimum Parasitics Ensuring Maximum
High-Frequency Performance
D Improved Op Amp Speed, Settling Time Accuracy
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signal
D Wideband Differential Amps
D High-Speed, Temp-Compensated,
Single-Ended Input Amps
D High-Speed Comparators
D Impedance Converters
DESCRIPTION
The U440/441 are matched pairs of JFETs mounted in a single
TO-71 package. This two-chip design reduces parasitics and
gives better performance at very high frequencies while
ensuring extremely tight matching. These devices are an
excellent choice for use as wideband differential amplifiers in
demanding test and measurement applications.
The hermetically-sealed TO-71 package is available with full
military screening per MIL-S-19500 (see Military Information).
For similar products in SO-8 packaging see the
SST440/SST441 data sheet. For low-noise options, see the
SST/U401 series data sheet. For low-leakage alternatives,
see the U421/423 data sheet.
TO-71
Top View
G
1
S
1
D
1
G
2
D
2
S
2
1
2
3
6
5
4
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage –25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-Gate Voltage "50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (
1
/
16
” from case for 10 sec.) 300_C. . . . . . . . . . . . . . . . . . .
Storage Temperature –65 to 200_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature –55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation : Per Side
a
250 mW. . . . . . . . . . . . . . . . . . . . . . . .
Total
b
500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
a. Derate 2 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C
U440/441
Vishay Siliconix
www.vishay.com
8-2
Document Number: 70251
S-04031—Rev. D, 04-Jun-01
SPECIFICATIONS (T
A
= 25_C UNLESS OTHERWISE NOTED)
Limits
U440 U441
Parameter Symbol Test Conditions Typ
a
Min Max Min Max Unit
Static
Gate-Source Breakdown Voltage V
(BR)GSS
I
G
= –1 mA, V
DS
= 0 V
–35 –25 –25
Gate-Source Cutoff Voltage V
GS(off)
V
DS
= 10 V, I
D
= 1 nA –3.5 –1 –6 –1 –6
V
Saturation Drain Current
b
I
DSS
V
DS
= 10 V, V
GS
= 0 V 15 6 30 6 30 mA
V
GS
= –15 V, V
DS
= 0 V –1 –500 –500 pA
Gate Reverse Current I
GSS
T
A
= 125_C
–2 nA
V
DG
= 10 V, I
D
= 5 mA –1 –500 –500 pA
Gate Operating Current I
G
T
A
= 125_C
–0.3 nA
Gate-Source Forward Voltage V
GS(F)
I
G
= 1 mA , V
DS
= 0 V 0.7 V
Dynamic
Common-Source
Forward Transconductance
g
fs
V
DS
= 10 V, I
D
= 5 mA
6 4.5 9 4.5 9 mS
Common-Source
Output Conductance
g
os
V
DS
= 10 V, I
D
= 5 mA
f = 1 kHz
70 200 200
mS
Common-Source
Input Capacitance
C
iss
V
DS
= 10 V, I
D
= 5 mA
3
Common-Source Reverse
Transfer Capacitance
C
rss
V
DS
= 10 V, I
D
= 5 mA
f = 1 MHz
1
pF
Equivalent Input
Noise Voltage
e
n
V
DS
= 10 V, I
D
= 5 mA
f = 10 kHz
4
nV⁄
√Hz
Matching
Differential Gate-Source Voltage
|
V
GS1
– V
GS2
|
V
DG
= 10 V, I
D
= 5 mA 6 10 20 mV
Gate-Source Voltage
Differential Change
with Temperature
D
|
V
GS1
– V
GS2
|
DT
V
DG
= 10 V, I
D
= 5 mA
T
A
= –55 to 125_C
20
mV/_C
Saturation Drain Current Ratio
c
I
DSS1
I
DSS2
V
DS
= 10 V, V
GS
= 0 V 0.97
Transconductance Ratio
c
g
fs1
g
fs2
V
DS
= 10 V, I
D
= 5 mA
f = 1 kHz
0.97
Common Mode Rejection Ratio CMRR V
DG
= 5 to 10 V, I
D
= 5 mA 85 dB
Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NZFD
b. Pulse test: PW v300 ms duty cycle v3%.
c. Assumes smaller value in the numerator.
U440/441
Vishay Siliconix
Document Number: 70251
S-04031—Rev. D, 04-Jun-01
www.vishay.com
8-3
TYPICAL CHARACTERISTICS (T
A
= 25_C UNLESS OTHERWISE NOTED)
50
0 –10–8–2
40
10
0
20
16
4
0
30
20
12
8
–4 –6
0 4 16 20812
Drain Current and Transconductance
vs. Gate-Source Cutoff Voltage
V
GS(off)
– Gate-Source Cutoff Voltage (V)
I
DSS
@ V
DS
= 10 V, V
GS
= 0 V
g
fs
@ V
DS
= 10 V, V
GS
= 0 V
f = 1 kHz
g
fs
I
DSS
g
fs
– Forward Transconductance (mS)
Gate Leakage Current
V
DG
– Drain-Gate Voltage (V)
0.1 pA
10 pA
1 pA
I
G(on)
@ I
D
I
GSS
@ 25_C
T
A
= 125_C
10 mA
1 mA
T
A
= 25_C
I
GSS
@ 125_C
1 mA
I
D
= 10 mA
– Gate Leakage
I
G
10
068210
8
6
2
0
4
4
Output Characteristics
V
DS
– Drain-Source Voltage (V)
– Drain Current (mA)
I
D
V
GS
= 0 V
–0.2 V
–0.4 V
–0.6 V
–0.8 V
–1.0 V
–1.2 V
V
GS(off)
= –2 V
5
0 0.2 0.8 1
4
1
0
2
3
0.4 0.6
Output Characteristics
V
DS
– Drain-Source Voltage (V)
– Drain Current (mA)
I
D
–0.2 V
–0.4 V
–0.6 V
–0.8 V
–1.0 V
–1.2 V
V
GS
= 0 V
V
GS(off)
= –2 V
15
0 0.2 0.8 1
12
3
0
9
6
0.4 0.6
Output Characteristics
V
DS
– Drain-Source Voltage (V)
– Drain Current (mA)
I
D
V
GS
= 0 V
–1.5 V
–0.5 V
–2.5 V
–1.0 V
–3.0 V
–3.5 V
–2.0 V
V
GS(off)
= –5 V
30
08210
24
6
0
18
12
46
Output Characteristics
V
DS
– Drain-Source Voltage (V)
– Drain Current (mA)
I
D
V
GS
= 0 V
–0.5 V
–2.5 V
–2.0 V
–3.0 V
–3.5 V
–1.0 V
–1.5 V
V
GS(off)
= –5 V
100 pA
1 nA
10 nA
100 nA
– Saturation Drain Current (mA)
I
DSS
P1-P3P4-P6P7-P7

U440-E3

Mfr. #:
Buy U440-E3
Manufacturer:
Vishay Semiconductors
Description:
JFET Dual Matched
Lifecycle:
New from this manufacturer.
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