MAX3453E–MAX3456E
±15kV ESD-Protected USB Transceivers
4 _______________________________________________________________________________________
Note 1: Parameters are 100% production tested at +25°C, unless otherwise noted. Limits over temperature are guaranteed by design.
Note 2: Guaranteed by design, not production tested.
Note 3: Production tested to +2.7V for V
L
< +3.0V.
Note 4: Including external 27Ω series resistor.
TIMING CHARACTERISTICS
(V
BUS
= +4.0V to +5.5V or V
TRM
= +3.0V to +3.6V, V
L
= +1.65V to +3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at V
BUS
= +5V, V
L
= +2.5V, and T
A
= +25°C.) (Note 1)
DRIVER CHARACTERISTICS (Full-Speed Mode, C
L
= 50pF)
Rise Time t
FR
10% to 90% of |V
OHD
- V
OLD
|, Figures 1, 6 4 20 ns
Fall Time t
FF
90% to 10% of |V
OHD
- V
OLD
|, Figures 1, 6 4 20 ns
Rise/Fall-Time Matching (Note 2)
t
FR
/ t
FF
Excluding the first transition from idle state,
Figures 1, 6
90 110 %
Output-Signal Crossover Voltage
(Note 2)
V
CRS_F
Excluding the first transition from idle state,
Figures 2, 6
1.3 2.0 V
t
PLH_DRV
Low-to-high transition, Figures 2, 6 18
Driver Propagation Delay
t
PHL_DRV
High-to-low transition, Figures 2, 6 18
ns
t
PHZ_DRV
High-to-off transition, Figure 3 20 ns
Driver Disable Delay
t
PLZ_DRV
Low-to-off transition, Figure 3 20 ns
t
PZH_DRV
Off-to-high transition, Figure 3 20 ns
Driver Enable Delay
t
PZL_DRV
Off-to-low transition, Figure 3 20 ns
DRIVER CHARACTERISTICS (low-speed mode, C
L
= 200pF to 600pF, MAX3454E/MAX3455E/MAX3456E)
Rise Time t
LR
10% to 90% of |V
OHD
- V
OLD
|, Figures 1, 6 75 300 ns
Fall Time t
LF
90% to 10% of |V
OHD
- V
OLD
|, Figures 1, 6 75 300 ns
Rise/Fall-Time Matching
t
LR
/ t
LF
Excluding the first transition from idle state,
Figures 1, 6
80 125 %
Output-Signal Crossover Voltage
V
CRS_L
Excluding the first transition from idle state,
Figures 2, 6
1.3 2.0 V
RECEIVER CHARACTERISTICS (C
L
= 15pF)
t
PLH_RCV
Low-to-high transition, Figures 4, 6 22
Differential Receiver Propagation
Delay
t
PHL_RCV
High-to-low transition, Figures 4, 6 22
ns
t
PLH_SE
Low-to-high transition, Figures 4, 6 12
Single-Ended Receiver
Propagation Delay
t
PHL_SE
High-to-low transition, Figures 4, 6 12
ns
t
PHZ_SE
High-to-off transition, Figure 5 15
Single-Ended Receiver Disable
Delay
t
PLZ_SE
Low-to-off transition, Figure 5 15
ns
t
PZH_SE
Off-to-high transition, Figure 5 15
Single-Ended Receiver Enable
Delay
t
PZL_SE
Off-to-low transition, Figure 5 15
ns
