AD2S1205YSTZ Datasheet AD2S1205WSTZ, ADW71205YSTZ, AD2S1205YSTZ | P10-P12

AD2S1205

Rev. A | Page 9 of 20

THEORY OF OPERATION

The AD2S1205’s operation is based on a Type II tracking closed-

loop principle. The digitally implemented tracking loop continually

tracks the position and velocity of the resolver without the need

for external convert and wait states. As the resolver moves through

a position equivalent to the least significant bit weighting, the

tracking loop output is updated by 1 LSB.

The converter tracks the shaft angle (θ) by producing an output

angle (ϕ) that is fed back and compared with the input angle

(θ); the difference between the two angles is the error, which is

driven towards 0 when the converter is correctly tracking the

input angle. To measure the error, S3 − S1 is multiplied by Cosϕ

and S2 − S4 is multiplied by Sinϕ to give

S4 S2for)(

S1S3for)(

−×

SinφCosθωtSinE

CosφSinθωtSinE

(2)

The difference is taken, giving

)()(

SinφCosθCosSinθωtSinE −

× (3)

This signal is demodulated using the internally generated

synthetic reference, yielding

)(

−

SinCosθCosSinθE (4)

Equation 4 is equivalent to E

Sin(θ − ϕ), which is approximately

equal to E

(θ − ϕ) for small values of θ − ϕ, where θ − ϕ is the

angular error.

The value E

(θ − ϕ) is the difference between the angular error

of the rotor and the digital angle output of the converter.

A phase-sensitive demodulator, some integrators, and a compen-

sation filter form a closed-loop system that seeks to null the

error signal. If this is accomplished, ϕ equals the resolver angle,

θ, within the rated accuracy of the converter. A Type II tracking

loop is used so that constant velocity inputs can be tracked

without inherent error.

For more information about the operation of the converter, see

the Circuit Dynamics section.

FAULT DETECTION CIRCUIT

The AD2S1205 fault detection circuit can sense loss of resolver

signals, out-of-range input signals, input signal mismatch, or

loss of position tracking; however, the position indicated by

the AD2S1205 may differ significantly from the actual shaft

position of the resolver.

MONITOR SIGNAL

The AD2S1205 generates a monitor signal by comparing the

angle in the position register to the incoming Sin and Cos signals

from the resolver. The monitor signal is created in a similar fashion

to the error signal (described in the Theory of Operation section).

The incoming Sinθ and Cosθ signals are multiplied by the Sin

and Cos of the output angle, respectively, and then these values

are added together:

)()( CosφCosθA2SinφSinθA1Monitor

×+×

(5)

where:

A1 is the amplitude of the incoming Sin signal (A1 × Sinθ).

A2 is the amplitude of the incoming Cos signal (A2 × Cosθ).

θ is the resolver angle.

ϕ is the angle stored in the position register.

Note that Equation 5 is shown after demodulation with the

carrier signal Sin(ωt) removed. Also note that for a matched

input signal (that is, a no fault condition), A1 is equal to A2.

When A1 is equal to A2 and the converter is tracking

(therefore, θ is equal to ϕ), the monitor signal output has a

constant magnitude of A1 (Monitor = A1 × (Sin

θ + Cos

θ) = A1),

which is independent of the shaft angle. When A1 does not

equal A2, the monitor signal magnitude alternates between A1

and A2 at twice the rate of the shaft rotation. The monitor

signal is used to detect degradation or loss of input signals.

LOSS OF SIGNAL DETECTION

Loss of signal (LOS) is detected when either resolver input (Sin

or Cos) falls below the specified LOS Sin/Cos threshold. The

AD2S1205 detects this by comparing the monitor signal to a

fixed minimum value. Without the use of external circuitry,

the AD2S1205 can detect the loss of up to three of the four

connections from the resolver. The addition of two external

68 kΩ resistors, as outlined in Figure 5, ensures that the loss of

all 4 connections, that is, complete removal of the resolver, may

also be detected. LOS is indicated by both DOS and LOT

latching as logic low outputs. The DOS and LOT pins are

reset to the no fault state by a rising edge of

SAMPLE

. The

LOS condition has priority over both the DOS and LOT

conditions, as shown in . LOS is indicated within 57°

of the angular output error (worst case).

Tabl e 4

AD2S1205

Rev. A | Page 10 of 20

SIGNAL DEGRADATION DETECTION

Degradation of signal (DOS) is detected when either resolver input

(Sin or Cos) exceeds the specified DOS Sin/Cos threshold. The

AD2S1205 detects this by comparing the monitor signal to a

fixed maximum value. In addition, DOS is detected when the

amplitudes of the Sin and Cos input signals are mismatched

by more than the specified DOS Sin/Cos mismatch. This is

identified because the AD2S1205 continuously stores the

minimum and maximum magnitude of the monitor signal in

internal registers and calculates the difference between these

values. DOS is indicated by a logic low on the DOS pin and is

not latched when the input signals exceed the maximum input

level. When DOS is indicated due to mismatched signals, the

output is latched low until a rising edge of

SAMPLE

resets the

stored minimum and maximum values. The DOS condition has

priority over the LOT condition, as shown in . DOS is

indicated within 33° of the angular output error (worst case).

Table 4

LOSS OF POSITION TRACKING DETECTION

Loss of tracking (LOT) is detected when

• The internal error signal of the AD2S1205 exceeds 5°.

• The input signal exceeds the maximum tracking rate.

• The internal position (at the position integrator) differs

from the external position (at the position register) by

more than 5°.

LOT is indicated by a logic low on the LOT pin and is not

latched. LOT has a 4° hysteresis and is not cleared until the

internal error signal or internal/external position mismatch

is less than 1°. When the maximum tracking rate is exceeded,

LOT is cleared only if the velocity is less than the maximum

tracking rate and the internal/external position mismatch is

less than 1°. LOT can be indicated for step changes in position

(such as after a

RESET

signal is applied to the AD2S1205), or

for accelerations of >~65,000 rps

. It is also useful as a built-in

test to indicate that the tracking converter is functioning

properly. The LOT condition has lower priority than both the

DOS and LOS conditions, as shown in . The LOT and

DOS conditions cannot be indicated at the same time.

Tabl e 4

Table 4. Fault Detection Decoding

Condition DOS Pin LOT Pin

Order of

Priority

Loss of Signal (LOS) 0 0 1

Degradation of Signal (DOS) 0 1 2

Loss of Tracking (LOT) 1 0 3

No Fault 1 1

RESPONDING TO A FAULT CONDITION

If a fault condition (LOS, DOS, or LOT) is indicated by the

AD2S1205, the output data is presumed to be invalid. Even

if a

RESET

SAMPLE

pulse releases the fault condition and

is not immediately followed by another fault, the output data

may be corrupted. As discussed previously, there are some fault

conditions with inherent latency. If the device fault is cleared,

there may be some latency in the resolver’s mechanical position

before the fault condition is reindicated.

When a fault is indicated, all output pins still provide data, although

the data may or may not be valid. The fault condition does not

force the parallel, serial, or encoder outputs to a known state.

Response to specific fault conditions is a system-level requirement.

The fault outputs of the AD2S1205 indicate that the device has

sensed a potential problem with either the internal or external

signals of the AD2S1205. It is the responsibility of the system

designer to implement the appropriate fault-handling schemes

within the control hardware and/or algorithm of a given appli-

cation based on the indicated fault(s) and the velocity or position

data provided by the AD2S1205.

FALSE NULL CONDITION

Resolver-to-digital converters that employ Type II tracking loops

based on the previously stated error equation (see Equation 4

in the Theory of Operation section) can suffer from a condition

known as a false null. This condition is caused by a metastable

solution to the error equation when θ − ϕ = 180°. The AD2S1205

is not susceptible to this condition because its hysteresis is

implemented external to the tracking loop. As a result of the

loop architecture chosen for the AD2S1205, the internal error

signal constantly has some movement (1 LSB per clock cycle);

therefore, in a metastable state, the converter moves to an

unstable condition within one clock cycle. This causes the tracking

loop to respond to the false null condition as if it were a 180°

step change in input position (the response time is the same, as

specified in the Dynamic Performance section of Table 1).

Therefore, it is impossible to enter the metastable condition

after the start-up sequence if the resolver signals are valid.

AD2S1205

Rev. A | Page 11 of 20

ON-BOARD PROGRAMMABLE SINUSOIDAL

OSCILLATOR

An on-board oscillator provides the sinusoidal excitation signal

(EXC) and its complement signal (

EXC

) to the resolver. The fre-

quency of this reference signal is programmable to four standard

frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) by using the

FS1 and FS2 pins (see ). FS1 and FS2 have internal pull-ups,

so the default frequency is 10 kHz. The amplitude of this signal

is centered on 2.5 V and has an amplitude of 3.6 V p-p.

Table 5

Table 5. Excitation Frequency Selection

Frequency Selection (kHz) FS1 FS2

10 1 1

12 1 0

15 0 1

20 0 0

The frequency of the reference signal is a function of the CLKIN

frequency. By decreasing the CLKIN frequency, the minimum

excitation frequency can also be decreased. This allows an

excitation frequency of 7.5 kHz to be set when using a CLKIN

frequency of 6.144 MHz, and it also decreases the maximum

tracking rate to 750 rps.

The reference output of the AD2S1205 requires an external buffer

amplifier to provide gain and additional current to drive the

resolver. See Figure 6 for a suggested buffer circuit.

The AD2S1205 also provides an internal synchronous reference

signal that is phase locked to its Sin and Cos inputs. Phase errors

between the resolver’s primary and secondary windings may

degrade the accuracy of the RDC and are compensated for by using

this synchronous reference signal. This also compensates for the

phase shifts due to temperature and cabling, and it eliminates the

need for an external preset phase-compensation circuit.

SYNTHETIC REFERENCE GENERATION

When a resolver undergoes a high rotation rate, the RDC tends

to act as an electric motor and produces speed voltages in

addition to the ideal Sin and Cos outputs. These speed voltages are

in quadrature to the main signal waveform. Moreover, nonzero

resistance in the resolver windings causes a nonzero phase shift

between the reference input and the Sin and Cos outputs. The

combination of the speed voltages and the phase shift causes a

tracking error in the RDC that is approximated by

FrequencyReference

RateRotation

ShiftPhaseError ×=

(6)

To compensate for the described phase error between the resolver

reference excitation and the Sin/Cos signals, an internal synthetic

reference signal is generated in phase with the reference frequency

carrier. The synthetic reference is derived using the internally

filtered Sin and Cos signals. It is generated by determining the

zero crossing of either the Sin or Cos (whichever signal is

larger), which improves phase accuracy, and evaluating the phase

of the resolver reference excitation. The synthetic reference reduces

the phase shift between the reference and Sin/Cos inputs to less

than 10° and can operate for phase shifts of ±45°.

CHARGE-PUMP OUTPUT

A 204.8 kHz square wave output with a 50% duty cycle is available

at the CPO pin of the AD2S1205. This square wave output can

be used for negative rail voltage generation or to create a V

rail.

CONNECTING THE CONVERTER

Ground is connected to the AGND and DGND pins (see Figure 5).

A positive power supply (V

) of 5 V dc ± 5% is connected to

the AV

and DV

pins, with typical values for the decoupling

capacitors being 10 nF and 4.7 μF. These capacitors are then

placed as close to the device pins as possible and are connected

to both AV

and DV

. If desired, the reference oscillator

frequency can be changed from the nominal value of 10 kHz

using FS1 and FS2. Typical values for the oscillator decoupling

capacitors are 20 pF, whereas typical values for the reference

decoupling capacitors are 10 μF and 0.01 μF. As outlined in the

Loss of Signal Detection section 68 kΩ resistors between the Sin

and SinLO inputs and the Cos and CosLO inputs can be used to

ensure loss of signal detection when all four inputs from resolver

are disconnected.

In this recommended configuration, the converter introduces a

REF

/2 offset in the Sin and Cos signal outputs from the resolver.

The SinLO and CosLO signals can each be connected to a different

potential relative to ground if the Sin and Cos signals adhere to the

recommended specifications. Note that because the EXC and

EXC

outputs are differential, there is an inherent gain of 2×.

shows a suggested buffer circuit. Capacitor C1 may be used in

parallel with Resistor R2 to filter out any noise that may exist on the

EXC and

Figure 6

EXC

outputs. Care should be taken when selecting the

cutoff frequency of this filter to ensure that phase shifts of the

carrier caused by the filter do not exceed the phase lock range

of the AD2S1205.

The gain of the circuit is

))1/(1()/(

ωC1R2R1R2nCarrierGai

×+×

−

(7)

and

⎟

⎠

⎞

⎜

⎝

⎛

××+×−

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

+×=

INREF

OUT

VωC1R2

VV ))1/(1(1

(8)

where:

ω is the radian frequency of the applied signal.

REF

, a dc voltage, is set so that V

OUT

is always a positive value,

eliminating the need for a negative supply.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD2S1205YSTZ

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