ADW71205YSTZ-RL Datasheet AD2S1205WSTZ, ADW71205YSTZ, AD2S1205YSTZ | P7-P9

AD2S1205

Rev. A | Page 6 of 20

06339-002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFOUT

REFBYP

CosLO

SinLO

AGND

EXC

Cos

Sin

RD 2

CS 3

SAMPLE 4

RDVEL 5

SOE 6

DB11/SO 7

DB10/SCL

DB9 9

DB8 10

DB7 11

RESET33

FS232

FS131

LOT30

DOS29

AD2S1205

TOP VIEW

(Not to Scale)

DIR

NM27

B26

A25

CPO24

DGND23

DB6

DB5

DB4

DB3

DGND

DB2

DB1

DB0

TALOUT

CLKIN

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 17 DV

Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1205. The

and DV

voltages ideally should be at the same potential and must not be more than 0.3 V apart, even

on a transient basis.

Edge-Triggered Logic Input. This pin acts as a frame synchronization signal and output enable. The output buffer is

enabled when CS

and RD are held low.

Chip Select. Active low logic input. The device is enabled when CS is held low.

SAMPLE

Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and

velocity registers, respectively, after a high-to-low transition on the SAMPLE

signal.

RDVEL

Read Velocity. Logic input. RDVEL input is used to select between the angular position register and the angular

velocity register. RDVEL

is held high to select the angular position register and low to select the angular

velocity register.

SOE

Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is

selected by holding the SOE

pin low, and the parallel interface is selected by holding the SOE pin high.

7 DB11/SO

Data Bit 11/Serial Data Output Bus. When the SOE

pin is high, this pin acts as DB11, a three-state data output pin

controlled by CS

and RD. When the SOE pin is low, this pin acts as SO, the serial data output bus controlled by CS

and RD

. The bits are clocked out on the rising edge of SCLK.

8 DB10/SCLK

Data Bit 10/Serial Clock. In parallel mode this pin acts as DB10, a three-state data output pin controlled by CS

and RD.

In serial mode this pin acts as the serial clock input.

9 to 15 DB9 to DB3

Data Bit 9 to Data Bit 3. Three-state data output pins controlled by CS

and RD.

16, 23 DGND

Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1205. All digital input

signals should be referred to this DGND voltage. Both of these pins can be connected to the AGND plane of a

system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V

apart, even on a transient basis.

18 to 20 DB2 to DB0

Data Bit 2 to Data Bit 0. Three-state data output pins controlled by CS

and RD.

21 XTALOUT

Crystal Output. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and

XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%.

22 CLKIN

Clock Input. To achieve the specified dynamic performance, an external crystal is recommended at the CLKIN and

XTALOUT pins. The position and velocity accuracy are guaranteed for a frequency range of 8.192 MHz ± 25%.

24 CPO

Charge-Pump Output. Analog output. A 204.8 kHz square wave output with a 50% duty cycle is available at the

CPO output pin. This square wave output can be used for negative rail voltage generation or to create a VCC rail.

25 A

Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format

input signals applied to the converter are valid.

AD2S1205

Rev. A | Page 7 of 20

Pin No. Mnemonic Description

26 B

Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format

input signals applied to the converter are valid.

27 NM

North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the

resolver format input signals applied to the converter are valid.

28 DIR

Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The

DIR output indicates the direction of the input rotation and is high for increasing angular rotation.

29 DOS

Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (Sin or Cos)

exceeds the specified DOS Sin/Cos threshold. See the Signal Degradation Detection section. DOS is indicated by a

logic low on the DOS pin and is not latched when the input signals exceed the maximum input level.

30 LOT

Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. See the Loss of

Signal Detection section.

31 FS1

Frequency Select 1. Logic input. FSI in conjunction with FS2 allows the frequency of EXC/EXC

to be programmed.

32 FS2

Frequency Select 2. Logic input. FS2 in conjunction with FS1 allows the frequency of EXC/EXC

to be programmed.

RESET

Reset. Logic input. The AD2S1205 requires an external reset signal to hold the RESET input low until V

is within

the specified operating range of 4.5 V to 5.5 V. See the section. Supply Sequencing and Reset

34 EXC

Excitiation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its

complement signal (EXC

) to the resolver. The frequency of this reference signal is programmable via the FS1 and FS2 pins.

EXC

Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal

(EXC) and its complement signal (EXC

) to the resolver. The frequency of this reference signal is programmable via

the FS1 and FS2 pins.

36, 42 AGND

Analog Ground. These pins are ground reference points for analog circuitry on the AD2S1205. All analog input

signals and any external reference signal should be referred to this AGND voltage. Both of these pins should be

connected to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

37 Sin Positive Analog Input of Differential Sin/SinLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.

38 SinLO Negative Analog Input of Differential Sin/SinLO Pair. The input range is 2.3 V p-p to 4.0 V p-p.

39 AV

Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1205. The

and DV

voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a

transient basis.

40 CosLO Negative Analog Input of Differential Cos/CosLO Pair.

41 Cos Positive Analog Input of Differential Cos/CosLO Pair.

43 REFBYP

Reference Bypass. Reference decoupling capacitors should be connected here. Typical recommended values are

10 μF and 0.01 μF.

44 REFOUT Voltage Reference Output, 2.39 V to 2.52 V.

AD2S1205

Rev. A | Page 8 of 20

RESOLVER FORMAT SIGNALS

06339-003

× Sin(ωt)

= V

× Sin(ωt) × Sin(θ)

(A) CLASSICAL RESOLVER

S1 S3

= V

× Sin(ωt) × Cos(θ)

× Sin(ωt)

= V

× Sin(ωt) × Sin(θ)

(B) VARIABLE RELUCTANCE RESOLVER

S1 S3

= V

× Sin(ωt) × Cos(θ)

Figure 3. Classical Resolver vs. Variable Reluctance Resolver

A classical resolver is a rotating transformer that typically has a

primary winding on the rotor and two secondary windings on

the stator. A variable reluctance resolver, on the other hand, has the

primary and secondary windings on the stator and no windings

on the rotor, as shown in Figure 3; however, the saliency in this

rotor design provides the sinusoidal variation in the secondary

coupling with the angular position. For both designs, the resolver

output voltages (S3 − S1, S2 − S4) are as follows:

SinθtSinES1S3

×ω=− )( (1)

CosθtSinES4S2

×ω=− )(

where:

θ is the shaft angle.

Sin(ωt) is the rotor excitation frequency.

is the rotor excitation amplitude.

The stator windings are displaced mechanically by 90° (see

Figure 3). The primary winding is excited with an ac reference.

The amplitude of subsequent coupling onto the secondary

windings is a function of the position of the rotor (shaft)

relative to the stator. The resolver therefore produces two

output voltages (S3 − S1, S2 − S4), modulated by the sine and

cosine of the shaft angle. Resolver format signals refer to the

signals derived from the output of a resolver, as shown in

Equation 1. Figure 4 illustrates the output format.

06339-004

0°

S2 – S4

(COSINE)

S3 – S1

(SINE)

R2 – R4

(REFERENCE)

90° 180°

270° 360°

Figure 4. Electrical Resolver Representation

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

ADW71205YSTZ-RL

Mfr. #:

Buy ADW71205YSTZ-RL

Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized 12-bit, 1000RPS Resolver-Digital Convert

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ADW71205YSTZ-RL

ADW71205YSTZ-RL

Products related to this Datasheet