1. General description
The PCK942C is a 1 : 18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS
output capabilities. The device is offered in two versions: the PCK942C has an LVCMOS
input clock, while the PCK942P has an LVPECL input clock. The 18 outputs are 2.5 V or
3.3 V LVCMOS compatible and feature the drive strength to drive 50 Ω series or parallel
terminated transmission lines. With output-to-output skews of 200 ps, the PCK942C is
ideal as a clock distribution chip for the most demanding of synchronous systems. The
2.5 V outputs also make the device ideal for supplying clocks for a higher performance
Pentium II microprocessor based design.
With a low output impedance of approximately 12 Ω, in both the HIGH and LOW logic
states, the output buffers of the PCK942C are ideal for driving series terminated
transmission lines. With an output impedance of 12 Ω the PCK942C can drive two series
terminated transmission lines from each output. This capability gives the PCK942C an
effective fan-out of 1 : 36. The PCK942C provides enough copies of low skew clocks for
most high performance synchronous systems.
The LVCMOS/LVTTL input of the PCK942C provides a more standard LVCMOS interface.
The OE pin will place the outputs into a high-impedance state. The OE pin has an internal
pull-up resistor.
The PCK942C is a single supply device. The V
CC
power pins require either 2.5 V or 3.3 V.
The 32-lead LQFP package was chosen to optimize performance, board space, and cost
of the device. The 32-lead LQFP package has a 7 mm × 7 mm body size with a
conservative 0.8 mm pin spacing.
2. Features
■ LVCMOS/LVTTL clock input
■ 2.5 V LVCMOS outputs for Pentium II microprocessor support
■ 150 ps maximum targeted output-to-output skew
■ Maximum output frequency of 250 MHz @ 3.3 V V
CC
■ 32-lead LQFP packaging
■ Single 3.3 V or 2.5 V supply voltage
PCK942C
Low voltage 1 : 18 clock distribution chip
Rev. 01 — 15 February 2006 Product data sheet
