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TC7126CPL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
2002-2012 Microchip Technology Inc. DS21458D-page 7
TC7126/A
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
(40-Pin PDIP)
Normal
(Reversed) Symbol Description
1 (40) V+ Positive supply voltage.
2 (39) D
1
Activates the D section of the units display.
3 (38) C
1
Activates the C section of the units display.
4 (37) B
1
Activates the B section of the units display.
5 (36) A
1
Activates the A section of the units display.
6 (35) F
1
Activates the F section of the units display.
7 (34) G
1
Activates the G section of the units display.
8 (33) E
1
Activates the E section of the units display.
9 (32) D
2
Activates the D section of the tens display.
10 (31) C
2
Activates the C section of the tens display.
11 (30) B
2
Activates the B section of the tens display.
12 (29) A
2
Activates the A section of the tens display.
13 (28) F
2
Activates the F section of the tens display.
14 (27) E
2
Activates the E section of the tens display.
15 (26) D
3
Activates the D section of the hundreds display.
16 (25) B
3
Activates the B section of the hundreds display.
17 (24) F
3
Activates the F section of the hundreds display.
18 (23) E
3
Activates the E section of the hundreds display.
19 (22) AB
4
Activates both halves of the 1 in the thousands display.
20 (21) POL Activates the negative polarity display.
21 (20) BP LCD Backplane drive output (TC7106A). Digital Ground (TC7107A).
22 (19) G
3
Activates the G section of the hundreds display.
23 (18) A
3
Activates the A section of the hundreds display.
24 (17) C
3
Activates the C section of the hundreds display.
25 (16) G
2
Activates the G section of the tens display.
26 (15) V- Negative power supply voltage.
27 (14) V
INT
The integrating capacitor should be selected to give the maximum voltage swing that
ensures component tolerance buildup will not allow the integrator output to saturate.
When analog common is used as a reference and the conversion rate is 3 readings
per second, a 0.047F capacitor may be used. The capacitor must have a low
dielectric constant to prevent rollover errors. See Section 6.3 “Integrating Capaci-
tor (CINT)”, Integrating Capacitor for additional details.
28 (13) V
BUFF
Integration resistor connection. Use a 180k resistor for a 200mV full-scale range
and a 1.8M resistor for a 2V full scale range.
29 (12) C
AZ
The size of the auto-zero capacitor influences system noise. Use a 0.33F capacitor
for 200mV full scale, and a 0.033F capacitor for 2V full scale. See Section 6.1
“Auto-Zero Capacitor (CAZ)”, Auto-Zero Capacitor for additional details.
30 (11) V
IN
- The analog LOW input is connected to this pin.
31 (10) V
IN
+ The analog HIGH input signal is connected to this pin.
32 (9) ANALOG
COMMON
This pin is primarily used to set the Analog Common mode voltage for battery opera-
tion, or in systems where the input signal is referenced to the power supply. It also
acts as a reference voltage source. See Section 7.3 “Analog Common (Pin 32)”,
Analog Common for additional details.
33 (8) C
REF
- See Pin 34.
TC7126/A
DS21458D-page 8 2002-2012 Microchip Technology Inc.
34 (7) C
REF
+A 0.1F capacitor is used in most applications. If a large Common mode voltage
exists (for example, the V
IN
- pin is not at analog common) and a 200mV scale is
used, a 1F capacitor is recommended and will hold the rollover error to 0.5 count.
35 (6) V
REF
- See Pin 36.
36 (5) V
REF
+ The analog input required to generate a full scale output (1999 counts). Place 100mV
between Pins 35 and 36 for 199.9mV full scale. Place 1V between Pins 35 and 36 for
2V full scale. See Section 6.6 “Reference Voltage Selection”, Reference Voltage
for additional information.
37 (4) TEST Lamp test. When pulled HIGH (to V+), all segments will be turned on and the display
should read -1888. It may also be used as a negative supply for externally
generated decimal points. See Section 7.4 “TEST (Pin 37)”, TEST for additional
information.
38 (3) OSC3 See Pin 40.
39 (2) OSC2 See Pin 40.
40 (1) OSC1 Pins 40, 39 and 38 make up the oscillator section. For a 48kHz clock (3 readings,
39 per second), connect Pin 40 to the junction of a 180k resistor and a 50pF
capacitor. The 180k resistor is tied to Pin 39 and the 50pF capacitor is tied to
Pin 38.
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number
(40-Pin PDIP)
Normal
(Reversed) Symbol Description
2002-2012 Microchip Technology Inc. DS21458D-page 9
TC7126/A
3.0 DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin PDIP.)
3.1 Dual Slope Conversion Principles
The TC7126A is a dual slope, integrating analog-to-
digital converter. An understanding of the dual slope
conversion technique will aid in following the detailed
TC7126/A operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
• Input Signal Integration
• Reference Voltage Integration (De-integration)
The input signal being converted is integrated for a
fixed time period (T
SI
). Time is measured by counting
clock pulses. An opposite polarity constant reference
voltage is then integrated until the integrator output
voltage returns to zero. The reference integration time
is directly proportional to the input signal (T
RI
) (see
Figure ).
FIGURE 3-1: Basic Dual Slope Converter
In a simple dual slope converter, a complete conver-
sion requires the integrator output to “ramp-up” and
“ramp-down.”
A simple mathematical equation relates the input
signal, reference voltage and integration time:
EQUATION 3-1:
For a constant V
IN
:
EQUATION 3-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. Noise
immunity is an inherent benefit. Noise spikes are inte-
grated or averaged to zero during integration periods.
Integrating ADCs are immune to the large conversion
errors that plague successive approximation convert-
ers in high noise environments. Interfering signals with
frequency components at multiples of the averaging
period will be attenuated. Integrating ADCs commonly
operate with the signal integration period set to a
multiple of the 50Hz/60Hz power line period (see
Figure 3-2).
FIGURE 3-2: Normal Mode Rejection of
Dual Slope Converter
+
–
REF
Voltage
Analog
Input
Signal
+
–
Display
Switch
Driver
Control
Logic
Integrator
Output
Clock
Counter
Polarity Control
Phase
Control
V
IN
» V
REF
V
IN
» 1.2 V
REF
Variable
Reference
Integrate
Time
Fixed
Signal
Integrate
Time
Integrator
Comparator
Where:
V
R
= Reference voltage
T
SI
= Signal integration time (fixed)
T
RI
= Reference voltage integration time (variable)
1
RC
T
SI
0
V
IN
(t)d
t
=
V
R
T
RI
RC
V
IN
V
R
T
RI
T
SI
-------=
30
20
10
0
Normal Mode Rejection (dB)
0.1/t 1/t 10/t
Input Frequency
t = Measurement Period
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

TC7126CPL

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