LTC1665/LTC1660
9
166560fa
TIMING DIAGRAM
D
IN
D
OUT
S/LD
SCK
A3
A3
A3 A2
A2 X1A1 X0
166560 F01
A1 X1
X0
t
2
t
8
t
9
t
11
t
5
t
7
t
6
t
1
t
3
t
4
Figure 1
OPERATION
Transfer Function
The transfer function is:
V
OUT(IDEAL)
=
k
256
⎛
⎝
⎜
⎞
⎠
⎟
V
REF
for theLTC1665
V
OUT(IDEAL)
=
k
1024
⎛
⎝
⎜
⎞
⎠
⎟
V
REF
for theLTC1660
where k is the decimal equivalent of the binary DAC input
code and V
REF
is the voltage at REF (Pin 6).
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent
and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.2V ≤ V
REF
≤ V
CC
+ 0.2V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 16) is in transition.
Serial Interface
Referring to Figure 2a (2b): With CS/LD held low, data
on the D
IN
input is shifted into the 16-bit shift register on
the positive edge of
SCK
. The 4-bit DAC address, A3-A0,
is loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word
and causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note:
SCK
must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the D
OUT
pin, which swings from GND to V
CC
. Data
appears on D
OUT
16 positive SCK edges after being ap-
plied to D
IN
.
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, D
IN
and
CS
/LD) by
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each D
OUT
(except the
last) to D
IN
of the next chip, forming a single 16m-bit
shift register. The SCK and
CS
/LD signals are common
to all chips in the chain. In use,
CS
/LD is held low while m
16-bit words are clocked to D
IN
of the first chip;
CS
/LD
is then pulled high, updating all of them simultaneously.
