MLX71121KLQ-AAA-000-RE Datasheet MLX71121KLQ-AAA-000-TU, MLX71121KLQ-AAA-000-SP, MLX71121KLQ-AAA-000-RE | P10-P12

MLX71121

300 to 930MHz

FSK/OOK Receiver

39010 71121 Page 10 of 29 Data Sheet

Rev. 012 Mar/15

1.14 Data Filter

The data filter is formed by the operational amplifier OA1, two internal 100k resistors and two external ca-

pacitors. It is implemented as a 2

order Sallen-Key filter. The low pass filter characteristic rejects noise at

higher frequencies and therefore leads to an increased sensitivity.

Fig. 6: Data filter

The filter’s pole locations can be set by the external capacitors CF1 and CF2. The cut-off frequency f

has to

be adjusted according to the transmission data rate R. It should be set to approximately 1.5 times the fastest

expected data rate. For a Butterworth filter characteristic, the data filter capacitors can be calculated as fol-

lows.

f100kπ2

CF1





CF1

CF2 

[kbit/s] R

NRZ

[kbit/s] fc [kHz] CF1 [pF] CF2 [pF]

0.6 1.2 0.9 2200 1000

1.2 2.4 1.8 1200 680

1.6 3.2 2.4 1000 470

2.4 4.8 3.6 680 330

3.3 6.6 5 470 220

4.8 9.6 7.2 330 150

6.0 12 9 220 100

1.15 Data Slicer

The purpose of the data slicer is to convert the filtered data signal into a digital output. It can therefore be

considered as an analog-to-digital converter. This is done by using the operational amplifier OA2 as a com-

parator that compares the data filter output with a threshold voltage. The threshold voltage can be derived in

two different ways from the data signal.

SLCSEL Description

0 Averaging detection mode

1 Peak detection mode

OA1

data filter

DF1 DF2

DF0

100k 100k

CF1

CF2

MLX71121

300 to 930MHz

FSK/OOK Receiver

39010 71121 Page 11 of 29 Data Sheet

Rev. 012 Mar/15

1.15.1 Averaging Detection Mode

The simplest configuration is the averaging or RC inte-

gration method. Here an on-chip 100k resistor togeth-

er with an external slicer capacitor (CSL) are forming an

RC low-pass filter. This way the threshold voltage au-

tomatically adjusts to the mean or average value of the

analog input voltage.

To create a stable threshold voltage, the cut-off fre-

quency of the low pass has to be lower than the lowest

signal frequency.

100k

CSL

AVG



AVG

1.5

τ 

A long string of zeros or ones, like in NRZ codes, can

cause a drift of the threshold. That’s why a Manchester

or other DC-free coding scheme works best.

The peak detectors are disabled during averaging de-

tection mode, and the output pins PDP and PDN are

pulled to ground (S4, S6 are closed).

Fig. 7: Data path in averaging detection mode

1.15.2 Peak Detection Mode

Peak detection mode has a general advantage over

averaging detection mode because of the part attack

and slow release times. Peak detection should be used

for all non-DC-free codes like NRZ. In this configuration

the threshold is generated by using the positive and

negative peak detectors. The slicer comparator thresh-

old is set to the midpoint between the high output and

the low output of the data filter by an on-chip resistance

divider. Two external capacitors (CP1, CP2) determine

the release times for the positive and negative enve-

lope. The two on-chip resistors provide a path for the

capacitors to discharge. This allows the peak detectors

to dynamically follow peak changes of the data filter

output voltage. The attack times are very short due to

the high peak detector load currents of about 500uA.

The decay time constant mainly depends on the longest

time period without bit polarity change. This corre-

sponds to the maximum number of consecutive bits with

the same polarity (N

MAX

100k

CP1/2

DECAY



NRZ

MAX

DECAY

τ 

Fig. 8: Data path in peak detection mode

If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are disa-

bled and the output of the positive peak detector (PDP) is connected to VEE (S4 is closed) and the output of

the negative peak detector (PDN) is connected to VCC (S5 is closed). This guarantees the correct biasing of

CP1 and CP2 during start-up.

CSL

PKDET+

PKDET

OA2

data slicer

PDP

SLC

100k

Control

logic

DTAO

CINT

VCC

PDN

data

filter

SLCSEL

switches

VCC

CP1

CP2

PKDET+

PKDET

OA2

data slicer

PDP

PDN

SLC

100k

VCC

Control

logic

DTAO

CINT

data

filter

SLCSEL

switches

MLX71121

300 to 930MHz

FSK/OOK Receiver

39010 71121 Page 12 of 29 Data Sheet

Rev. 012 Mar/15

1.16 Data Output and Noise Cancellation Filter

The data output pin DTAO delivers the demodulated data signal which can be further processed by a noise

cancellation filter (NCF). The NCF can be disabled if pin CINT is connected to ground. In this case the

multiplexer (MUX) connects the receiver output DTAO directly to the data slicer output.

Fig. 9: Data output and noise filter

The noise cancellation filter can suppress random pulses in the data output which are shorter than t

min

RZNRZ

min

105.71015

1015CF3











The NCF can also operate as a muting circuit. So if the RF input signal is below sensitivity level (or if no RF

signal is applied) then the data output will go to a constant DC level (either HIGH or LOW). This can be

achieved by setting the bandwidth of the preceding data filter (sec 1.13) about 10 times higher than the

bandwidth of the NCF. Further the data filter cutoff frequency must be higher than the data rate, so the noise

pulses are shorter than the shortest data pulse. Otherwise, the NCF will not be able to distinguish between

noise and data pulses.

Having the NCF activated is a good means for reducing the computing power of the microcontroller that fol-

lows the receiver IC for further data processing.

In contrast to a conventional muting (or squelch) circuit, this topology does not need the RSSI signal for level

indication. The filtering process is done by means of an analogue integrator. The cut-off frequency of the

NCF is set by the external capacitor connected to pin CINT. This capacitor C

should be set according to

the maximum data rate. Below table provides some recommendations..

During receiver start-up a sequencer checks if pin CINT is connected to a capacitor or to ground. The maxi-

mum value of C

should not exceed 12nF. This defines the lowest data rate that can be processed if the

noise cancellation filter is activated.

[kbit/s] R

NRZ

[kbit/s] C

[nF]

0.6 1.2 12

1.2 2.4 6.8

1.6 3.2 4.7

2.4 4.8 3.3

3.3 6.6 2.2

4.8 9.6 1.5

6.0 12 1.2

CF3

data slicer

output

CINT

NCF

noise cancellation filter

MUX

DTAO

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MLX71121KLQ-AAA-000-RE

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RF Receiver Wireless sensing

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MLX71121KLQ-AAA-000-RE

MLX71121KLQ-AAA-000-RE

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