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MC74VHCT240AMELG

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 7
1 Publication Order Number:
MC74VHCT240A/D
MC74VHCT240A
Octal Bus Buffer/Line Driver
Inverting with 3−State Outputs
The MC74VHCT240A is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHCT240A is an inverting 3−state buffer, and has two
active−low output enables. This device is designed to be used with
3−state memory address drivers, etc.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT240A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
Features
• High Speed: t
PD
= 5.6 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 4.5 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 1.1 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 110 FETs or 27.5 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
20
1
TSSOP−20
SUFFIX DT
CASE 948E
SOIC−20WB
SUFFIX DW
CASE 751D
VHCT
240A
ALYWG
G
1
1
20
1
VHCT240A
AWLYYWWG
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
MC74VHCT240A
http://onsemi.com
2
Figure 1. Logic Diagram
DATA
INPUTS
A1
A2
A3
A4
B1
B2
B3
B4
17
15
13
11
8
6
4
218
16
14
12
9
7
5
3
YB4
YB3
YB2
YB1
YA4
YA3
YA2
YA1
INVERTING
OUTPUTS
OUTPUT
ENABLES
OEA
OEB
1
19
Figure 2. Pin Assignment
A3
A2
YB4
A1
OEA
GND
YB1
A4
YB2
YB3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
YA2
B4
YA1
OEB
V
CC
B1
YA4
B2
YA3
B3
OEA, OEB A, B YA, YB
L
L
H
L
H
X
H
L
Z
INPUTS OUTPUTS
FUNCTION TABLE
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage Output in 3−State
High or Low State
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current − 20 mA
I
OK
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
) ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 75 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating − SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 4.5 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage Output in 3−State
High or Low State
0
0
5.5
V
CC
V
T
A
Operating Temperature − 40 + 85
_C
t
r
, t
f
Input Rise and Fall Time V
CC
=5.0V ±0.5V 0 20 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHCT240A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= − 40 to 85°C
Unit
Min Typ Max Min Max
V
IH
Minimum High−Level Input
Voltage
4.5 to 5.5 2.0 2.0 V
V
IL
Maximum Low−Level Input
Voltage
4.5 to 5.5 0.8 0.8 V
V
OH
Minimum High−Level Output
Voltage V
in
= V
IH
or V
IL
I
OH
= − 50mA
4.5 4.4 4.5 4.4 V
I
OH
= − 8mA 4.5 3.94 3.80
V
OL
Maximum Low−Level Output
Voltage V
in
= V
IH
or V
IL
I
OL
= 50mA
4.5 0.0 0.1 0.1 V
I
OL
= 8mA 4.5 0.36 0.44
I
in
Maximum Input Leakage Current V
in
= 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0
mA
I
OZ
Maximum 3−State Leakage
Current
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ±
0.25
± 2.5
mA
I
CC
Maximum Quiescent Supply
Current
V
in
= V
CC
or GND 5.5 4.0 40.0
mA
I
CCT
Quiescent Supply Current Per Input: V
IN
= 3.4V
Other Input: V
CC
or GND
5.5 1.35 1.50 mA
I
OPD
Output Leakage Current V
OUT
= 5.5V 0 0.5 5.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbo
l
Parameter Test Conditions
T
A
= 25°C T
A
= − 40 to 85°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Maximum Propagation Delay
A to YA
or B to YB
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
5.6
6.1
7.8
8.8
1.0
1.0
9.0
10.0
ns
t
PZL
,
t
PZH
Output Enable Time
OEA
to YA or OEB to YB
V
CC
= 5.0 ± 0.5V C
L
= 15pF
R
L
= 1kW C
L
= 50pF
7.7
8.2
10.4
11.4
1.0
1.0
12.0
13.0
ns
t
PLZ
,
t
PHZ
Output Disable Time
OEA
to YA or OEB to YB
V
CC
= 5.0 ± 0.5V C
L
= 50pF
R
L
= 1kW
8.8 11.4 1.0 13.0 ns
t
OSLH
,
t
OSHL
Output to Output Skew V
CC
= 5.0 ± 0.5V C
L
= 50pF
(Note 1)
1.0 1.0 ns
C
in
Maximum Input Capacitance 4 10 10 pF
C
out
Maximum Three−State Output
Capacitance (Output in
High−Impedance State)
9 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0V
pF
19
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
− t
PLHn
|, t
OSHL
= |t
PHLm
− t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/8 (per bit). C
PD
is used to determine the no−load
dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
Symbo
l
Parameter
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9 1.1 V
V
OLV
Quiet Output Minimum Dynamic V
OL
− 0.9 − 1.1 V
V
IHD
Minimum High Level Dynamic Input Voltage 2.0 V
V
ILD
Maximum Low Level Dynamic Input Voltage 0.8 V
P1-P3P4-P6

MC74VHCT240AMELG

Mfr. #:
Buy MC74VHCT240AMELG
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 5V Octal 3-State Inverting
Lifecycle:
New from this manufacturer.
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