1/10August 2001
■ HIGH SPEED :
f
MAX
= 48MHz (TYP.) at V
CC
= 4.5V
■ LOW POWER DISSIPATION:
I
CC
=2µA(MAX.) at T
A
=25°C
■ COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
DESCRIPTION
The M74HCT74 is an high speed CMOS DUAL D
TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C
2
MOS technology.
A signal on the D INPUT (nD) is transferred on the
Q OUTPUT during the positive going transition of
the clock pulse. CLEAR (CLR
) and PRESET (PR)
are independent of the clock and accomplished by
a low on the appropriate input.
The M74HCT74 is designed to directly interface
HSC
2
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
DIP M74HCT74B1R
SOP M74HCT74M1R M74HCT74RM13TR
TSSOP M74HCT74TTR
TSSOPDIP SOP
