Detailed Description
The MAX1069 analog-to-digital converter (ADC) uses
successive-approximation conversion (SAR) tech-
niques and on-chip track-and-hold (T/H) circuitry to
capture and convert an analog signal to a serial 14-bit
digital output.
The MAX1069 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the inter-
nal reference or by an externally applied reference volt-
age ranging from 1V to V
AVDD
.
The flexible 2-wire serial interface provides easy con-
nection to microcontrollers (µCs) and supports data
rates up to 1.7MHz. Figure 3 shows the simplified func-
tional diagram for the MAX1069 and Figure 4 shows the
typical application circuit.
Power Supply
To maintain a low-noise environment, the MAX1069
provides separate analog and digital power-supply
inputs. The analog circuitry requires a +5V supply and
consumes only 900µA at sampling rates up to
58.6ksps. The digital supply voltage accepts voltages
from +2.7V to +5.5V to ensure compatibility with low-
voltage ASICs. The MAX1069 wakes up in shutdown
mode when power is applied irrespective of the V
AVDD
and V
DVDD
sequence.
Analog Input and Track/Hold
The MAX1069 analog input contains a track-and-hold
(T/H) capacitor, T/H switches, comparator, and a
switched capacitor digital-to-analog converter (DAC)
(Figure 5).
As shown in Figure 11c, the MAX1069 acquisition peri-
od is the two clock cycles prior to the conversion peri-
od. The T/H switches are normally in the hold position.
During the acquisition period the T/H switches are in
the track position and C
T/H
charges to the analog input
signal. Before a conversion begins, the T/H switches
move to the hold position retaining the charge on C
T/H
as a sample of the analog input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 14-bit resolution. This is equiva-
lent to transferring a charge of 35pF × (V
AIN
- V
AGNDS
)
from C
T/H
to the binary-weighted capacitive DAC,
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________ 11
Pin Description
Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1µF capacitor.
Connect REFADJ to AVDD to disable the internal bandgap reference and reference-buffer amplifier.
Reference Buffer Output and External Reference Input. Bypass to AGND with a 10µF capacitor
when using the internal reference.
