MAX1069AEUD+T Datasheet MAX1069BEUD+, MAX1069AEUD+, MAX1069AEUD+T | P13-P15

for f

SCL

= 1.7MHz. R

SOURCE

is calculated with the fol-

lowing equation:

where R

SOURCE

is the analog input source impedance,

SCL

is the maximum system SCL frequency, N is 14

(the number of bits of resolution), C

is 35pF (the sum

of C

T/H

and input stray capacitance), and R

is 800Ω

(the T/H switch resistances).

To improve the input-signal bandwidth under AC

conditions, drive AIN with a wideband buffer

(> 4MHz) that can drive the ADC’s input capacitance

and settle quickly (see the

Input Buffer

section).

An RC filter at AIN reduces the input track-and-hold

switching transient by providing charge for C

T/H

Analog Input Bandwidth

The MAX1069 features input-tracking circuitry with a

4MHz small-signal bandwidth. The 4MHz input band-

width makes it possible to digitize high-speed transient

events and measure periodic signals with bandwidths

exceeding the ADC’s sampling rate by using under-

sampling techniques. Use anti-alias filtering to avoid

high-frequency signals being aliased into the frequency

band of interest.

Analog Input Range and Protection

Internal ESD (electrostatic discharge) protection diodes

clamp AIN, REF, and REFADJ to AV

and

AGNDS/AGND (Figure 6). These diodes allow the ana-

log inputs to swing from (V

AGND

- 0.3V) to (V

AVDD

0.3V) without causing damage to the device. For accu-

rate conversions, the inputs must not go more than

50mV beyond their rails.

If the analog inputs exceed 300mV beyond their

rails, limit the current to 2mA.

Internal Clock

The MAX1069 contains an internal 4MHz oscillator that

drives the SAR conversion clock. During conversion, SCL

is held low (clock stretching). An internal register stores

data when the conversion is in progress. When the

MAX1069 releases SCL, the master reads the conversion

results at any clock rate up to 1.7MHz (Figure 11).

Digital Interface

The MAX1069 features an I

C-compatible, 2-wire serial

interface consisting of a bidirectional serial data line

(SDA) and a serial clock line (SCL). SDA and SCL facili-

tate bidirectional communication between the

MAX1069 and the master at rates up to 1.7MHz. The

master (typically a microcontroller) initiates data trans-

fer on the bus and generates SCL.

SDA and SCL require pullup resistors (500Ω or greater,

Figure 4). Optional resistors (24Ω) in series with SDA

and SCL protect the device inputs from high-voltage

spikes on the bus lines. Series resistors also minimize

crosstalk and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL clock

cycle. Nine clock cycles are required to transfer the

data into or out of the MAX1069. The data on SDA must

remain stable during the high period of the SCL clock

pulse as changes in SDA while SCL is high are control

signals (see the

START and STOP Conditions

section).

Both SDA and SCL idle high.

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), a high-to-low transition on SDA with SCL high.

The master terminates a transmission with a STOP con-

dition (P), a low-to-high transition on SDA while SCL is

high (Figure 7). The STOP condition frees the bus and

places all devices in F/S mode (see the

Bus Timing

section). Use a repeated START condition (Sr) in place

fIn

(

)

SOURCE

SCL

≤

×××

−

MAX1069

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

______________________________________________________________________________________ 13

Figure 5. Equivalent Input Circuit

T/H

AIN

AGNDS

CAPACITIVE

DAC

REF

TRACK

HOLD

TRACK

HOLD

TRACK

SOURCE

ANALOG

SIGNAL

SOURCE

*MINIMIZE R

SOURCE

TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (C

T/H

) TO

CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (t

ACQ

MAX1069

Figure 6. Internal Protection Diodes

AIN

REFADJ

AVDD

AGND

REF

AGNDS

MAX1069

of a STOP condition to leave the bus active and in its

current timing mode (see the

HS-Mode

section).

Acknowledge Bits

Successful data transfers are acknowledged with an

acknowledge bit (A) or a not-acknowledge bit (A). Both

the master and the MAX1069 (slave) generate acknowl-

edge bits. To generate an acknowledge, the receiving

device must pull SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and

keep it low during the high period of the clock pulse

(Figure 8). To generate a not acknowledge, the receiver

allows SDA to be pulled high before the rising edge of

the acknowledge-related clock pulse and leaves it high

during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer happens if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the master should reattempt com-

munication at a later time.

Slave Address

A master initiates communication with a slave device by

issuing a START condition followed by a slave address

byte. As shown in Figure 9, the slave address byte con-

sists of 7 address bits and a read/write bit (R/W). When

idle, the MAX1069 continuously waits for a START con-

dition followed by its slave address. When the

MAX1069 recognizes its slave address, it acquires the

analog input signal and prepares for conversion. The

first three bits (MSBs) of the slave address have been

factory programmed and are always 011. Connecting

ADD3–ADD0 to DVDD or DGND, programs the last four

bits (LSBs) of the slave address high or low.

Since the MAX1069 does not require setup or configu-

ration, the least significant bit (LSB) of the address byte

(R/W) controls power-down. In external reference mode

(REFADJ = AV

), R/W is a don’t care. In internal refer-

ence mode, setting R/W = 1 places the device in nor-

mal operation and setting R/W = 0 powers down the

internal reference following the conversion (see the

Internal Reference Shutdown

section).

After receiving the address, the MAX1069 (slave)

issues an acknowledge by pulling SDA low for one

clock cycle.

Bus Timing

At power-up, the MAX1069 bus timing defaults to fast

mode (F/S-mode), allowing conversion rates up to

19ksps. The MAX1069 must operate in high-speed

mode (HS-mode) to achieve conversion rates up to

58.6ksps. Figure 1 shows the bus timing for the

MAX1069 2-wire interface.

HS-Mode

At power-up, the MAX1069 bus timing is set for F/S-

mode. The master selects HS-mode by addressing all

devices on the bus with the HS-mode master code 0000

1XXX (X = don’t care). After successfully receiving the

HS-mode master code, the MAX1069 issues a not

acknowledge allowing SDA to be pulled high for one

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

14 ______________________________________________________________________________________

Figure 8. Acknowledge Bits

12 8 9

ACKNOWLEDGE

NOT ACKNOWLEDGE

SCL

SDA

Figure 7. START and STOP Conditions

SPSr

SCL

SDA

clock cycle (Figure 10). After the not acknowledge, the

MAX1069 is in HS-mode. The master must then send a

repeated START followed by a slave address to initiate

HS-mode communication. If the master generates a

STOP condition, the MAX1069 returns to F/S-mode.

Data Byte (Read Cycle)

Initiate a read cycle to begin a conversion. A read

cycle begins with the master issuing a START condition

followed by seven address bits and a read bit (R/W).

The standard I

C-compatible interface requires that

R/W = 1 to read from a device, however, since the

MAX1069 does not require setup or configuration, the

read mode is inherent and R/W controls power-down

(see the

Internal Reference Shutdown

section). If the

address byte is successfully received, the MAX1069

(slave) issues an acknowledge and begins conversion.

As seen in Figure 11, the MAX1069 holds SCL low dur-

ing conversion. When the conversion is complete, SCL

is released and the master can clock data out of the

device. The most significant byte of the conversion is

available first and contains D13 to D6. The least signifi-

cant byte contains D5 to D0 plus two trailing sub bits

S1 and S0. Data can be continuously converted as long

as the master acknowledges the conversion results.

Issuing a not acknowledge frees the bus allowing the

master to generate a STOP or repeated START.

Applications Information

Power-On Reset

When power is first applied, internal power-on reset cir-

cuitry activates the MAX1069 in shutdown. When the

internal reference is used, allow 12ms for the reference

to settle when C

REF

= 10µF and C

REFADJ

= 0.1µF.

Automatic Shutdown

The MAX1069 automatic shutdown reduces the supply

current to less than 0.6µA between conversions. The

MAX1069 I

C-compatible interface is always active.

When the MAX1069 receives a valid slave address the

device powers up. The device is then powered down

again when the conversion is complete. The automatic

shutdown function does not change with internal or

external reference. When the internal reference is cho-

sen, the internal reference remains active between con-

versions unless internal reference shutdown is requested

(see the

Internal Reference Shutdown

section).

Internal Reference Shutdown

The R/W bit of the slave address controls the MAX1069

internal reference shutdown. In external reference

mode (REFADJ = AVDD), R/W is a don’t care. In inter-

nal reference mode, setting R/W = 1 places the device

in normal operation and setting R/W = 0 prepares the

internal reference for shutdown.

MAX1069

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

______________________________________________________________________________________ 15

Figure 10. F/S-Mode to HS-Mode Transfer

123

000

894567

01XXX

F/S-MODE

HS-MODE

SDA

Figure 9. MAX1069 Slave Address Byte

SCL

SDA

123

110

894567

ADD3 ADD2 ADD1 ADD0

R/W

ACKNOWLEDGE

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MAX1069AEUD+T

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MAX1069AEUD+T

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