OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NCV7344D13R2G

P1-P3P4-P6P7-P9P10-P12P13-P13
NCV7344
www.onsemi.com
10
Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table
ISO 11898−2:2016 Specification NCV7344
Datasheet
Parameter Notation Symbol
Dominant output characteristics
Single ended voltage on CAN_H V
CAN_H
V
o(dom)(CANH)
Single ended voltage on CAN_L V
CAN_L
V
o(dom)(CANL)
Differential voltage on normal bus load V
Diff
V
o(dom)(diff)
Differential voltage on effective resistance during arbitration V
Diff
V
o(dom)(diff)_arb
Differential voltage on extended bus load range (optional) V
Diff
V
o(dom)(diff)
Driver symmetry
Driver symmetry V
SYM
V
o(dom)(sym)
Driver output current
Absolute current on CAN_H I
CAN_H
I
o(SC)(CANH)
Absolute current on CAN_L I
CAN_L
I
o(SC)(CANL)
Receiver output characteristics, bus biasing active
Single ended output voltage on CAN_H V
CAN_H
V
o(rec)(CANH)
Single ended output voltage on CAN_L V
CAN_L
V
o(rec)(CANL)
Differential output voltage V
Diff
V
o(rec)(diff)
Receiver output characteristics, bus biasing inactive
Single ended output voltage on CAN_H V
CAN_H
V
o(off)(CANH)
Single ended output voltage on CAN_L V
CAN_L
V
o(off)(CANL)
Differential output voltage V
Diff
V
o(off)(diff)
Optional transmit dominant timeout
Transmit dominant timeout, long t
dom
t
dom(TxD)
Transmit dominant timeout, short t
dom
NA
Static receiver input characteristics, bus biasing active
Recessive state differential input voltage range V
Diff
V
i(rec)(diff)_NM
Dominant state differential input voltage range V
Diff
V
i(dom)(diff)_NM
Static receiver input characteristics, bus biasing inactive
Recessive state differential input voltage range V
Diff
V
i(rec)(diff)_LP
Dominant state differential input voltage range V
Diff
V
i(dom)(diff)_LP
Receiver input resistance
Differential internal resistance R
Diff
R
i(diff)
Single ended internal resistance R
CAN_H
R
CAN_L
R
i(cm)(CANH)
R
i(cm)(CANL)
Receiver input resistance matching
Matching a of internal resistance m
R
R
i(cm)(m)
Implementation loop delay requirement
Loop delay t
Loop
t
pd_rd
t
pd_dr
Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s t
Bit(Bus)
t
Bit(Vi(diff))
Received recessive bit width @ 2 Mbit/s t
Bit(RXD)
t
Bit(RxD)
NCV7344
www.onsemi.com
11
Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table
Parameter SymbolNotation
Receiver timing symmetry @ 2 Mbit/s
Dt
Rec
D
tRec
Optional implementation data signal timing requirements for use with bit rates above 2 Mbit/s and up to 5 Mbit/s
Transmitted recessive bit width @ 5 Mbit/s t
Bit(Bus)
t
Bit(Vi(diff))
Transmitted recessive bit width @ 5 Mbit/s t
Bit(RXD)
t
Bit(RxD)
Received recessive bit width @ 5 Mbit/s
Dt
Rec
Dt
Rec
Maximum ratings of V
CAN_H
, V
CAN_L
and V
Diff
Maximum rating V
Diff
V
Diff
V
CANH−CANL
General maximum rating V
CAN_H
and V
CAN_L
V
CAN_H
V
CAN_L
V
CANH
V
CANL
Optional: Extended maximum rating V
CAN_H
and V
CAN_L
V
CAN_H
V
CAN_L
NA
Maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L I
CAN_H
I
CAN_L
I
LI
Bus biasing control timings
CAN activity filter time, long t
Filter
t
wake_filt
CAN activity filter time, short t
Filter
t
wake_filt
Wake−up timeout, short t
Wake
NA
Wake−up timeout, long t
Wake
t
wake_to
Timeout for bus inactivity (Required for selective wake−up implementation only) t
Silence
NA
Bus Bias reaction time (Required for selective wake−up implementation only) t
Bias
NA
DEVICE ORDERING INFORMATION (High Speed Low Power CAN, CANFD Transceiver)
Part Number
Long FT Short FT
Vio NC
Temperature
Range
Package Shipping
†
NCV7344D10R2G X X
−40°C to +150°C
SOIC 150 8 GREEN (Matte
Sn, JEDEC MS−012)
(Pb−Free)
3000 / Tape &
Reel
NCV7344D13R2G X X
NCV7344AD10R2G X X
NCV7344AD13R2G X X
NCV7344MW0R2G X X
DFN 8
Wettable Flank
(Pb−Free)
NCV7344MW3R2G X X
NCV7344AMW0R2G X X
NCV7344AMW3R2G X X
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV7344
www.onsemi.com
12
PACKAGE DIMENSIONS
SOIC−8
CASE 751AZ
ISSUE B
7.00
8X
0.76
8X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
14
85
SEATING
PLANE
DETAIL A
0.10 C
A1
DIM MIN MAX
MILLIMETERS
h 0.25 0.41
A --- 1.75
b 0.31 0.51
L 0.40 1.27
e 1.27 BSC
c 0.10 0.25
A1 0.10 0.25
L2
M
0.25 A-B
b8X
C
D
A
B
C
TOP VIEW
SIDE VIEW
0.25 BSC
E1 3.90 BSC
E 6.00 BSC
D
e
D
0.20 C
0.10 C
2X
NOTE 6
NOTES 4&5
NOTES 4&5
SIDE VIEW
END VIEW
E E1
D
0.10 C D
D
NOTES 3&7
NOTE 6
NOTE 8
A
A2
A2 1.25 ---
D 4.90 BSC
H
SEATING
PLANE
DETAIL A
L
C
L2
h
45 CHAMFER5
c
NOTE 7
P1-P3P4-P6P7-P9P10-P12P13-P13

NCV7344D13R2G

Mfr. #:
Buy NCV7344D13R2G
Manufacturer:
ON Semiconductor
Description:
CAN Interface IC HS LP CANFD TRANSC (VIO)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet