NCT275
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8
SERIAL INTERFACE
Control of the NCT275 is carried out via the
SMBus/I
2
Ccompatible serial interface. The NCT275 is
connected to this bus as a slave device, under the control of
a master device.
Serial Bus Address
Control of the NCT275 is carried out via the serial bus.
The NCT275 is connected to this bus as a slave device under
the control of a master device.
There are two NCT275 device options called NCT275A
and NCT275B. Each device supports two possible addresses
depending on Ball A2 (named A1) is connected high or low.
The NCT275 has a 7ïbit serial address. The four MSBs are
fixed and set to 1001 while the 3 LSBs can be configured by
the user using Ball A2 (named A1). The ball A2 can be
connected to VDD or ground.
Table 9. NCT275A SERIAL BUS ADDRESS
OPTIONS
Ball A2 I
2
C Address
0 0x49
1 0x4B
Table 10. NCT275B SERIAL BUS ADDRESS
OPTIONS
Ball A2 I
2
C Address
0 0x48
1 0x4A
The NCT275 also features a SMBus/I
2
C timeout function
whereby the SMBus/I
2
C interface times out after 25 ms of
no activity on the SDA line. After this time, the NCT275
resets the SDA line back to its idle state (high impedance)
and waits for the next start condition.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing
a start condition, defined as a high to low
transition on the serial data line SDA, while the
serial clock line SCL remains high. This indicates
that an address/data stream is going to follow. All
slave peripherals connected to the serial bus
respond to the start condition and shift in the next
eight bits, consisting of a 7ïbit address (MSB first)
plus a read/write (R/W) bit, which determines the
direction of the data transfer i.e. whether data is
written to, or read from, the slave device. The
peripheral with the address corresponding to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the acknowledge bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is a zero then the
master writes to the slave device. If the R/W bit is
a one then the master reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
acknowledge bit from the receiver of data.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, since a lowïtoïhigh
transition when the clock is high can be interpreted
as a stop signal.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the tenth
clock pulse to assert a stop condition. In read
mode, the master overrides the acknowledge bit by
pu pulls the data line high during the low period
before the ninth clock pulse. This is known as no
acknowledge. The master takes the data line low
during the low period before the tenth clock pulse,
then high during the tenth clock pulse to assert a
stop condition.
Any number of bytes of data can be transferred over the
serial bus in one operation. However, it is not possible to mix
read and write in one operation because the type of operation
is determined at the beginning and cannot subsequently be
changed without starting a new operation.
WRITING DATA
There are two types of writes used in the NCT275:
Setting up the Address Pointer Register for a Register
Read
To read data from a particular register, the address pointer
register must hold the address of the register being read. To
configure the address pointer register a single write
operation (shown in Figure 5). It consists of the device
address followed by the address being written to the address
pointer register. This will then be followed by a read
operation.
Writing Data to a Register
Due to the different size registers used by the NCT275,
there are two types of write operations. One is for the 8 bit
wide configuration register and the other for the 16 bit wide
limit registers.
Figure 6 shows the sequence required to write to the
configuration register. It consists of the device address, the
data register being written to and the data being written the
selected register.
The two temperature limit registers (T
HYST
and T
OS
) are
16 bits wide and require two data bytes to be written to these
registers. This sequence is shown in Figure 7. It consists of
the device address, the data register being written to and the
two data byes being written to the selected register.
