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74F620PC

P1-P3P4-P6
© 1999 Fairchild Semiconductor Corporation DS009577 www.fairchildsemi.com
April 1988
Revised August 1999
74F620 • 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs
74F620 • 74F623
Inverting Octal Bus Transceiver with 3-STATE Outputs
General Description
These devices are octal bus transceivers designed for
asynchronous two-way data flow between the A and B bus-
ses. Both busses are capable of sinking 64 mA and have 3-
STATE outputs. Dual enable pins (GAB, G
BA) allow data
transmission from the A bus to the B bus or from the B bus
to the A bus. The 74F620 is an inverting option of the
74F623.
Features
■ Designed for asynchronous two-way data flow between
busses
■ Outputs sink 64 mA
■ Dual enable inputs control direction of data flow
■ Guaranteed 4000V minimum ESD protection
■ 74F620 is an inverting option of the 74F623
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol Connection Diagram
FAST is a registered trademark of Fairchild Semiconductor Corporation
Order Number Package Number Package Description
74F620PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F623SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F623PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
74F620 • 74F623
Unit Loading/Fan Out
Functional Description
The enable inputs GAB and GBA control whether data is
transmitted from the A bus to the B bus or from the B bus to
the A bus. If both G
BA and GAB are disabled (GBA HIGH
and GAB LOW), the outputs are in the high impedance
state and data is stored at the A and B busses. When G
BA
is active LOW, B data is sent to the A bus. When GAB is
active HIGH, data from the A bus is sent to the B bus. If
both enable inputs are active (G
BA LOW and GAB HIGH)
B data is sent to the A bus while A data is sent to the B bus.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
Logic Diagrams
74F620
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F623
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
GBA, GAB Enable Inputs 1.0/1.0 20 µA/−0.6 mA
A
0
–A
7
A Inputs or 3.5/1.083 70 µA/−0.4 mA
3-STATE Outputs 150/40 −3 mA/64 mA
B
0
–B
7
B Inputs or 3.5/1.083 70 µA/−0.4 mA
3-STATE Outputs 150/40 −3 mA/64 mA
Enable Inputs Operation
G
BA GAB 74F620 74F623
LLB
Data to A Bus B Data to A Bus
HHA
Data to B Bus A Data to B Bus
HL Z Z
LHB
Data to A Bus, B Data to A Bus,
A
Data to B Bus A Data to B Bus
3 www.fairchildsemi.com
74F620 • 74F623
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min I
IN
= −18 mA (Non I/O Pins)
V
OH
Output HIGH
10% V
CC
2.0 V Min I
OH
= −15 mA (A
n
, B
n
)
Voltage
V
OL
Output LOW
10% V
CC
0.55 V Min I
OL
= 64 mA (A
n
, B
n
)
Voltage
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V (GBA, GAB)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max V
IN
= 5.5V (A
n
, B
n
)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Tes t All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max V
IN
= 0.5V (Non I/O Pins)
I
IH
+ I
OZH
Output Leakage Current 70 µAMaxV
OUT
= 2.7V (A
n
, B
n
)
I
IL
+ I
OZL
Output Leakage Current −650 µAMaxV
OUT
= 0.5V (A
n
, B
n
)
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current (74F620) 82 mA Max V
O
= HIGH, V
IN
= 0.2V
I
CCL
Power Supply Current (74F620) 82 mA Max V
O
= LOW
I
CCZ
Power Supply Current (74F620) 95 mA Max V
O
= HIGH Z
I
CCH
Power Supply Current (74F623) 65 mA Max V
O
= HIGH
I
CCL
Power Supply Current (74F623) 82 mA Max V
O
= LOW, V
IN
= 0.2V
I
CCZ
Power Supply Current (74F623) 85 mA Max V
O
= HIGH Z
P1-P3P4-P6

74F620PC

Mfr. #:
Buy 74F620PC
Manufacturer:
ON Semiconductor
Description:
IC TRANSCVR INVERT 5.5V 20DIP
Lifecycle:
New from this manufacturer.
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