NJW1504V-TE1

NJW1504/1508
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TEST CIRCUIT
16
HF
GND
VCC1
VCC3
BS3
BS2
BS1
BS0
XTAL
ADRS
SDA
SCL
OSC OUT
VCC2
AMP OUT
CP
15 14 13 12 11 10 9
87654321
4MHz
5V
100
34V
VS3
5V
2mV
1kHz
VS2
2.5V
VS1
4.7V or 0.3V
COUNTER
5V
50
SG
-20dBm
1n
18p
OSC OUT
SCLSDA
270
316k
NJW1504/1508
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I
2
C bus Protocols
The input information, which consists of chip address and next two or four byte data, is received by I
2
C bus
receiver. The allowable I
2
C bus protocols are as follows.
(1) STA CA CB BB STO
(2) STA CA D1 D2 STO
(3) STA CA CB BB D1 D2 STO
(4) STA CA D1 D2 CB BB STO
STA: Start Condition
STO: Stop Condition
CA: Chip Address
CB: Control Byte
BB: Band switch Byte
D1: Divider Byte 1
D2: Divider Byte 2
For suitable circuit operation,5-byte data should have chip address, 2-byte control data, band data, and 2-byte
divider byte. Following chip address. 2-byte data is received. For distinction of each data, first and third data
byte has a function bit. As function bit, divider byte has 1 and control/band data has 0.
1-7
9
SDA
SCL
STA ADDRESS R/W
1 -7
ACK DATA
8
8
9 9
ACK
ACK
STO
NJW1504/1508
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Data Format
Parameter Symbol MSB LSB
Chip Address CA 1 1 0 0 0 CA1 CA0 0 A
Divider Byte 1 D1 0 N14 N13 N12 N11 N10 N9 N8 A
Divider Byte 2 D2 N7 N6 N5 N4 N3 N2 N1 N0 A
Control Byte CB 1 CP T2 T1 T0 RD1 RD0 × A
Band switch Byte BB × × × × BS3 BS2 BS1 BS0 A
· Data specifications
× : don’t care ;0 or 1
CA1, CA0 : Programmable address bits
ADRS Voltage CA1 CA0
Always valid 0 1
0 to 0.1 Vcc1
0 0
0.4 Vcc1 to 0.6 Vcc1
1 0
0.9 Vcc1 to Vcc1
1 1
BS0 to BS3 : Band switch buffers Control bits, BSn=1 then ON
N0 to N14 : Control of Programmable divider bits, N14=MSB N0=LSB
Dividing ratio : N=2
14
×N14+2
13
× N13+······ +2
1
×N1+N0
Maximum division ratio 32767
Minimum division ratio 256
CP : Charge Pump Current
CP Charge Pump Current Conditions
1 280µA Normal, Default
0 60µA Test
T0 to T2 :Test mode bits
T0,T1,T2 :Phase Comparator Output bits
T2 T1 T0 Phase Comparator, Band Switch Conditions
0 0 × Normal Output Normal, Default
1 0 1 Phase Comparator (High Impedance) Test
1 1 0 Phase Comparator (Sink) Test
1 1 1
Phase Comparator (Source)
Test
RD1,RD0 : Reference Divider bits
RD1 RD2 Reference Divider Conditions
× 0 640
1 1 512 Default
0 1 1024
(Note)
Default : Power on reset

NJW1504V-TE1

Mfr. #:
Manufacturer:
NJR (New Japan Radio)
Description:
Clock Synthesizer / Jitter Cleaner PLL Syn w/ I2C
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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